arch-arm,cpu: Introduce a getEMI virtual method on StaticInst.

[gem5.git] / src / mem / Bridge.py

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 62dfb73517cb112e69c642d696f8ca0ba1173d6f..b4eb1d0db177133eac9c8f76c17512417b2738a9 100644 (file)
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -35,19 +35,25 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ali Saidi
-#          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.ClockedObject import ClockedObject
 
-class Bridge(MemObject):
+class Bridge(ClockedObject):
     type = 'Bridge'
-    slave = SlavePort('Slave port')
-    master = MasterPort('Master port')
-    req_size = Param.Int(16, "The number of requests to buffer")
-    resp_size = Param.Int(16, "The number of responses to buffer")
+    cxx_header = "mem/bridge.hh"
+
+    mem_side_port = RequestPort("This port sends requests and "
+                                "receives responses")
+    master   = DeprecatedParam(mem_side_port,
+                              '`master` is now called `mem_side_port`')
+    cpu_side_port = ResponsePort("This port receives requests and "
+                                 "sends responses")
+    slave    = DeprecatedParam(cpu_side_port,
+                               '`slave` is now called `cpu_side_port`')
+
+    req_size = Param.Unsigned(16, "The number of requests to buffer")
+    resp_size = Param.Unsigned(16, "The number of responses to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")
     ranges = VectorParam.AddrRange([AllMemory],
                                    "Address ranges to pass through the bridge")