mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / Bridge.py

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 5f2cc9f40ae912fe51706913c6e6899cbb16df6e..e488871a436f9fc63605067265e7e6859e4ab0ce 100644 (file)
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -47,8 +47,8 @@ class Bridge(MemObject):
     cxx_header = "mem/bridge.hh"
     slave = SlavePort('Slave port')
     master = MasterPort('Master port')
-    req_size = Param.Int(16, "The number of requests to buffer")
-    resp_size = Param.Int(16, "The number of responses to buffer")
+    req_size = Param.Unsigned(16, "The number of requests to buffer")
+    resp_size = Param.Unsigned(16, "The number of responses to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")
     ranges = VectorParam.AddrRange([AllMemory],
                                    "Address ranges to pass through the bridge")