Cache: Remove dangling doWriteback declaration

[gem5.git] / src / mem / Bridge.py

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 38b344613b68a962d04cb62d1c18b699087ff29d..ea8684e1bba6e25f7b70fa937c0811aedb9c57fb 100644 (file)
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -31,8 +31,8 @@ from MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
-    slave = Port('Slave port')
-    master = Port('Master port')
+    slave = SlavePort('Slave port')
+    master = MasterPort('Master port')
     req_size = Param.Int(16, "The number of requests to buffer")
     resp_size = Param.Int(16, "The number of requests to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")