Cache: Remove dangling doWriteback declaration

[gem5.git] / src / mem / Bridge.py

diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index b48e1684d7db257965b449525855a2525cc2bd89..ea8684e1bba6e25f7b70fa937c0811aedb9c57fb 100644 (file)
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -31,16 +31,12 @@ from MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
-    side_a = Port('Side A port')
-    side_b = Port('Side B port')
-    req_size_a = Param.Int(16, "The number of requests to buffer")
-    req_size_b = Param.Int(16, "The number of requests to buffer")
-    resp_size_a = Param.Int(16, "The number of requests to buffer")
-    resp_size_b = Param.Int(16, "The number of requests to buffer")
+    slave = SlavePort('Slave port')
+    master = MasterPort('Master port')
+    req_size = Param.Int(16, "The number of requests to buffer")
+    resp_size = Param.Int(16, "The number of requests to buffer")
     delay = Param.Latency('0ns', "The latency of this bridge")
     nack_delay = Param.Latency('0ns', "The latency of this bridge")
     write_ack = Param.Bool(False, "Should this bridge ack writes")
-    filter_ranges_a = VectorParam.AddrRange([],
-            "What addresses shouldn't be passed through the side of the bridge")
-    filter_ranges_b = VectorParam.AddrRange([],
-            "What addresses shouldn't be passed through the side of the bridge")
+    ranges = VectorParam.AddrRange([AllMemory],
+                                   "Address ranges to pass through the bridge")