Mem: Use deque instead of list for bus retries

[gem5.git] / src / mem / Bus.py

diff --git a/src/mem/Bus.py b/src/mem/Bus.py
index 247a1fe310d832df74207f6fed84d4b33baa3584..447fc723e5ab16136cc692fa39b06143a2204f51 100644 (file)
--- a/src/mem/Bus.py
+++ b/src/mem/Bus.py
@@ -1,4 +1,16 @@
-# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -25,25 +37,37 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Nathan Binkert
+#          Andreas Hansson
 
-from m5 import build_env
-from m5.params import *
-from m5.proxy import *
 from MemObject import MemObject
+from m5.params import *
+
+class BaseBus(MemObject):
+    type = 'BaseBus'
+    abstract = True
+    slave = VectorSlavePort("vector port for connecting masters")
+    master = VectorMasterPort("vector port for connecting slaves")
+    # Override the default clock
+    clock = '1GHz'
+    header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
+    width = Param.Unsigned(8, "bus width (bytes)")
+    block_size = Param.Unsigned(64, "The default block size if not set by " \
+                                    "any connected module")
+
+    # The default port can be left unconnected, or be used to connect
+    # a default slave port
+    default = MasterPort("Port for connecting an optional default slave")
+
+    # The default port can be used unconditionally, or based on
+    # address range, in which case it may overlap with other
+    # ports. The default range is always checked first, thus creating
+    # a two-level hierarchical lookup. This is useful e.g. for the PCI
+    # bus configuration.
+    use_default_range = Param.Bool(False, "Perform address mapping for " \
+                                       "the default port")
 
-if build_env['FULL_SYSTEM']:
-    from Device import BadAddr
+class NoncoherentBus(BaseBus):
+    type = 'NoncoherentBus'
 
-class Bus(MemObject):
-    type = 'Bus'
-    port = VectorPort("vector port for connecting devices")
-    bus_id = Param.Int(0, "blah")
-    clock = Param.Clock("1GHz", "bus clock speed")
-    width = Param.Int(64, "bus width (bytes)")
-    responder_set = Param.Bool(False, "Did the user specify a default responder.")
-    block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.")
-    if build_env['FULL_SYSTEM']:
-        responder = BadAddr(pio_addr=0x0, pio_latency="1ps")
-        default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.")
-    else:
-        default = Port("Default port for requests that aren't handled by a device.")
+class CoherentBus(BaseBus):
+    type = 'CoherentBus'