class BaseBus(MemObject):
type = 'BaseBus'
abstract = True
+ cxx_header = "mem/bus.hh"
slave = VectorSlavePort("vector port for connecting masters")
master = VectorMasterPort("vector port for connecting slaves")
header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
class NoncoherentBus(BaseBus):
type = 'NoncoherentBus'
+ cxx_header = "mem/noncoherent_bus.hh"
class CoherentBus(BaseBus):
type = 'CoherentBus'
+ cxx_header = "mem/coherent_bus.hh"