mem-cache: Fix setting prefetch bit

[gem5.git] / src / mem / CommMonitor.py

diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index ba871357d2b7658d5479e6c1f37b6f75c05398ba..851e5a327e1a1caeb50ce5ddc4971874cd8ae41d 100644 (file)
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -32,36 +32,29 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Thomas Grass
-#          Andreas Hansson
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from System import System
+from m5.objects.System import System
+from m5.SimObject import SimObject
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
-class CommMonitor(MemObject):
+class CommMonitor(SimObject):
     type = 'CommMonitor'
     cxx_header = "mem/comm_monitor.hh"
 
     system = Param.System(Parent.any, "System that the monitor belongs to.")
 
     # one port in each direction
-    master = MasterPort("Master port")
-    slave = SlavePort("Slave port")
-
-    # Boolean to enable or disable the trace. Writes to an a file named based on
-    # SimObject hierarchy.
-    trace_enable = Param.Bool(False, "Enable trace capture")
-
-    # Boolean to compress the trace or not.
-    trace_compress = Param.Bool(True, "Enable trace compression")
-
-    # packet trace output file, disabled by default
-    trace_file = Param.String("", "Packet trace output file")
+    mem_side_port = RequestPort("This port sends requests and "
+                                "receives responses")
+    master   = DeprecatedParam(mem_side_port,
+                              '`master` is now called `mem_side_port`')
+    cpu_side_port = ResponsePort("This port receives requests and "
+                                 "sends responses")
+    slave    = DeprecatedParam(cpu_side_port,
+                              '`slave` is now called `cpu_side_port`')
 
     # control the sample period window length of this monitor
     sample_period = Param.Clock("1ms", "Sample period for histograms")