mem: Include WriteLineReq in cache demand stats

[gem5.git] / src / mem / CommMonitor.py

diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index 4e8cfe270aaf30677aa78b102d008d448cc14d96..aa8da62edc5a29d163b83611fb2cca972bf59ce0 100644 (file)
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -53,9 +53,6 @@ class CommMonitor(MemObject):
     master = MasterPort("Master port")
     slave = SlavePort("Slave port")
 
-    # packet trace output file, disabled by default
-    trace_file = Param.String("", "Packet trace output file")
-
     # control the sample period window length of this monitor
     sample_period = Param.Clock("1ms", "Sample period for histograms")