cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / CommMonitor.py

diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index 3f9106cc44e47e28952ca1c5fde8b39533b37ffa..d6324372255946ebf40f66b22702d81f44830c5a 100644 (file)
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -37,21 +37,22 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.proxy import *
+from m5.objects.System import System
+from m5.SimObject import SimObject
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
-class CommMonitor(MemObject):
+class CommMonitor(SimObject):
     type = 'CommMonitor'
     cxx_header = "mem/comm_monitor.hh"
 
+    system = Param.System(Parent.any, "System that the monitor belongs to.")
+
     # one port in each direction
     master = MasterPort("Master port")
     slave = SlavePort("Slave port")
 
-    # packet trace output file, disabled by default
-    trace_file = Param.String("", "Packet trace output file")
-
     # control the sample period window length of this monitor
     sample_period = Param.Clock("1ms", "Sample period for histograms")