cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / CommMonitor.py

diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index ba871357d2b7658d5479e6c1f37b6f75c05398ba..d6324372255946ebf40f66b22702d81f44830c5a 100644 (file)
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -38,12 +38,12 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from System import System
+from m5.objects.System import System
+from m5.SimObject import SimObject
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
-class CommMonitor(MemObject):
+class CommMonitor(SimObject):
     type = 'CommMonitor'
     cxx_header = "mem/comm_monitor.hh"
 
@@ -53,16 +53,6 @@ class CommMonitor(MemObject):
     master = MasterPort("Master port")
     slave = SlavePort("Slave port")
 
-    # Boolean to enable or disable the trace. Writes to an a file named based on
-    # SimObject hierarchy.
-    trace_enable = Param.Bool(False, "Enable trace capture")
-
-    # Boolean to compress the trace or not.
-    trace_compress = Param.Bool(True, "Enable trace compression")
-
-    # packet trace output file, disabled by default
-    trace_file = Param.String("", "Packet trace output file")
-
     # control the sample period window length of this monitor
     sample_period = Param.Clock("1ms", "Sample period for histograms")