cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / DRAMCtrl.py

diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index fa04c9f397a2b6632fe8ecb7353ce4c75d4c58ae..14db3d3c9d7bc775345a70a1a69c6dae8a728ab9 100644 (file)
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -46,8 +46,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from AbstractMemory import *
-from QoSMemCtrl import *
+from m5.objects.AbstractMemory import *
+from m5.objects.QoSMemCtrl import *
 
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served
@@ -135,6 +135,10 @@ class DRAMCtrl(QoSMemCtrl):
     # to be instantiated for a multi-channel configuration
     channels = Param.Unsigned(1, "Number of channels")
 
+    # Enable DRAM powerdown states if True. This is False by default due to
+    # performance being lower when enabled
+    enable_dram_powerdown = Param.Bool(False, "Enable powerdown states")
+
     # For power modelling we need to know if the DRAM has a DLL or not
     dll = Param.Bool(True, "DRAM has DLL or not")