# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2013 Amin Farmahini-Farahani
+# Copyright (c) 2015 University of Kaiserslautern
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
#
# Authors: Andreas Hansson
# Ani Udipi
+# Omar Naji
+# Matthias Jung
from m5.params import *
from AbstractMemory import *
IDD5 = '220mA'
VDD = '1.5V'
+# A single HMC-2500 x32 model based on:
+# [1] DRAMSpec: a high-level DRAM bank modelling tool
+# developed at the University of Kaiserslautern. This high level tool
+# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
+# estimate the DRAM bank latency and power numbers.
+# [2] A Logic-base Interconnect for Supporting Near Memory Computation in the
+# Hybrid Memory Cube (E. Azarkhish et. al)
+# Assumed for the HMC model is a 30 nm technology node.
+# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
+# layers).
+# Each layer has 16 vaults and each vault consists of 2 banks per layer.
+# In order to be able to use the same controller used for 2D DRAM generations
+# for HMC, the following analogy is done:
+# Channel (DDR) => Vault (HMC)
+# device_size (DDR) => size of a single layer in a vault
+# ranks per channel (DDR) => number of layers
+# banks per rank (DDR) => banks per layer
+# devices per rank (DDR) => devices per layer ( 1 for HMC).
+# The parameters for which no input is available are inherited from the DDR3
+# configuration.
+# This configuration includes the latencies from the DRAM to the logic layer of
+# the HMC
+class HMC_2500_x32(DDR3_1600_x64):
+ # size of device
+ # two banks per device with each bank 4MB [2]
+ device_size = '8MB'
+
+ # 1x32 configuration, 1 device with 32 TSVs [2]
+ device_bus_width = 32
+
+ # HMC is a BL8 device [2]
+ burst_length = 8
+
+ # Each device has a page (row buffer) size of 256 bytes [2]
+ device_rowbuffer_size = '256B'
+
+ # 1x32 configuration, so 1 device [2]
+ devices_per_rank = 1
+
+ # 4 layers so 4 ranks [2]
+ ranks_per_channel = 4
+
+ # HMC has 2 banks per layer [2]
+ # Each layer represents a rank. With 4 layers and 8 banks in total, each
+ # layer has 2 banks; thus 2 banks per rank.
+ banks_per_rank = 2
+
+ # 1250 MHz [2]
+ tCK = '0.8ns'
+
+ # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz
+ tBURST = '3.2ns'
+
+ # Values using DRAMSpec HMC model [1]
+ tRCD = '10.2ns'
+ tCL = '9.9ns'
+ tRP = '7.7ns'
+ tRAS = '21.6ns'
+
+ # tRRD depends on the power supply network for each vendor.
+ # We assume a tRRD of a double bank approach to be equal to 4 clock
+ # cycles (Assumption)
+ tRRD = '3.2ns'
+
+ # activation limit is set to 0 since there are only 2 banks per vault layer.
+ activation_limit = 0
+
+ # Values using DRAMSpec HMC model [1]
+ tRFC = '59ns'
+ tWR = '8ns'
+ tRTP = '4.9ns'
+
+ # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8
+ # ns (Assumption)
+ tCS = '0.8ns'
+
+ # Value using DRAMSpec HMC model [1]
+ tREFI = '3.9us'
+
+ # Set default controller parameters
+ page_policy = 'close'
+ write_buffer_size = 8
+ read_buffer_size = 8
+ addr_mapping = 'RoCoRaBaCh'
+ min_writes_per_switch = 8
+
# A single DDR3-2133 x64 channel refining a selected subset of the
# options for the DDR-1600 configuration, based on the same DDR3-1600
# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept
# constraints incurred by the bank groups
banks_per_rank = 16
+ # override the default buffer sizes and go for something larger to
+ # accommodate the larger bank count
+ write_buffer_size = 128
+ read_buffer_size = 64
+
# 1200 MHz
tCK = '0.833ns'
# Assume 2 cycles
tRTW = '2ns'
+# A single HBM x128 interface (one command and address bus), with
+# default timings based on data publically released
+# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014),
+# IDD measurement values, and by extrapolating data from other classes.
+# Architecture values based on published HBM spec
+# A 4H stack is defined, 2Gb per die for a total of 1GB of memory.
+class HBM_1000_4H_x128(DRAMCtrl):
+ # HBM gen1 supports up to 8 128-bit physical channels
+ # Configuration defines a single channel, with the capacity
+ # set to (full_ stack_capacity / 8) based on 2Gb dies
+ # To use all 8 channels, set 'channels' parameter to 8 in
+ # system configuration
+
+ # 128-bit interface legacy mode
+ device_bus_width = 128
+
+ # HBM supports BL4 and BL2 (legacy mode only)
+ burst_length = 4
+
+ # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack;
+ # with 8 channels, 128MB per channel
+ device_size = '128MB'
+
+ device_rowbuffer_size = '2kB'
+
+ # 1x128 configuration
+ devices_per_rank = 1
+
+ # HBM does not have a CS pin; set rank to 1
+ ranks_per_channel = 1
+
+ # HBM has 8 or 16 banks depending on capacity
+ # 2Gb dies have 8 banks
+ banks_per_rank = 8
+
+ # depending on frequency, bank groups may be required
+ # will always have 4 bank groups when enabled
+ # current specifications do not define the minimum frequency for
+ # bank group architecture
+ # setting bank_groups_per_rank to 0 to disable until range is defined
+ bank_groups_per_rank = 0
+
+ # 500 MHz for 1Gbps DDR data rate
+ tCK = '2ns'
+
+ # use values from IDD measurement in JEDEC spec
+ # use tRP value for tRCD and tCL similar to other classes
+ tRP = '15ns'
+ tRCD = '15ns'
+ tCL = '15ns'
+ tRAS = '33ns'
+
+ # BL2 and BL4 supported, default to BL4
+ # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns
+ tBURST = '4ns'
+
+ # value for 2Gb device from JEDEC spec
+ tRFC = '160ns'
+
+ # value for 2Gb device from JEDEC spec
+ tREFI = '3.9us'
+
+ # extrapolate the following from LPDDR configs, using ns values
+ # to minimize burst length, prefetch differences
+ tWR = '18ns'
+ tRTP = '7.5ns'
+ tWTR = '10ns'
+
+ # start with 2 cycles turnaround, similar to other memory classes
+ # could be more with variations across the stack
+ tRTW = '4ns'
+
+ # single rank device, set to 0
+ tCS = '0ns'
+
+ # from MemCon example, tRRD is 4ns with 2ns tCK
+ tRRD = '4ns'
+
+ # from MemCon example, tFAW is 30ns with 2ns tCK
+ tXAW = '30ns'
+ activation_limit = 4
+
+ # 4tCK
+ tXP = '8ns'
+
+ # start with tRFC + tXP -> 160ns + 8ns = 168ns
+ tXS = '168ns'
+
+# A single HBM x64 interface (one command and address bus), with
+# default timings based on HBM gen1 and data publically released
+# A 4H stack is defined, 8Gb per die for a total of 4GB of memory.
+# Note: This defines a pseudo-channel with a unique controller
+# instantiated per pseudo-channel
+# Stay at same IO rate (1Gbps) to maintain timing relationship with
+# HBM gen1 class (HBM_1000_4H_x128) where possible
+class HBM_1000_4H_x64(HBM_1000_4H_x128):
+ # For HBM gen2 with pseudo-channel mode, configure 2X channels.
+ # Configuration defines a single pseudo channel, with the capacity
+ # set to (full_ stack_capacity / 16) based on 8Gb dies
+ # To use all 16 pseudo channels, set 'channels' parameter to 16 in
+ # system configuration
+
+ # 64-bit pseudo-channle interface
+ device_bus_width = 64
+
+ # HBM pseudo-channel only supports BL4
+ burst_length = 4
+
+ # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack;
+ # with 16 channels, 256MB per channel
+ device_size = '256MB'
+
+ # page size is halved with pseudo-channel; maintaining the same same number
+ # of rows per pseudo-channel with 2X banks across 2 channels
+ device_rowbuffer_size = '1kB'
+
+ # HBM has 8 or 16 banks depending on capacity
+ # Starting with 4Gb dies, 16 banks are defined
+ banks_per_rank = 16
+
+ # reset tRFC for larger, 8Gb device
+ # use HBM1 4Gb value as a starting point
+ tRFC = '260ns'
+
+ # start with tRFC + tXP -> 160ns + 8ns = 168ns
+ tXS = '268ns'
# Default different rank bus delay to 2 CK, @1000 MHz = 2 ns
tCS = '2ns'
tREFI = '3.9us'
projects / gem5.git / blobdiff