mem-cache: Add match functions to QueueEntry

[gem5.git] / src / mem / DRAMCtrl.py

diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index 3145751cc7b80ab790efe81a56ab769802a5fa4a..93ea7d56fdc9be2e5d74c5d9b505444303eb94f9 100644 (file)
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2016 ARM Limited
+# Copyright (c) 2012-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -45,7 +45,9 @@
 #          Erfan Azarkhish
 
 from m5.params import *
-from AbstractMemory import *
+from m5.proxy import *
+from m5.objects.AbstractMemory import *
+from m5.objects.QoSMemCtrl import *
 
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served
@@ -68,7 +70,7 @@ class PageManage(Enum): vals = ['open', 'open_adaptive', 'close',
 # that aims to model the most important system-level performance
 # effects of a DRAM without getting into too much detail of the DRAM
 # itself.
-class DRAMCtrl(AbstractMemory):
+class DRAMCtrl(QoSMemCtrl):
     type = 'DRAMCtrl'
     cxx_header = "mem/dram_ctrl.hh"
 
@@ -183,6 +185,13 @@ class DRAMCtrl(AbstractMemory):
     # for CAS-to-CAS delay for bursts to different bank groups
     tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
 
+    # Write-to-Write delay for bursts to the same bank group
+    # only utilized with bank group architectures; set to 0 for default case
+    # This will be used to enable different same bank group delays
+    # for writes versus reads
+    tCCD_L_WR = Param.Latency(Self.tCCD_L,
+        "Same bank group Write to Write delay")
+
     # time taken to complete one refresh cycle (N rows in all banks)
     tRFC = Param.Latency("Refresh cycle time")