ruby: handle llsc accesses through CacheEntry, not CacheMemory

[gem5.git] / src / mem / DRAMCtrl.py

diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index ef187a31ca2b4d2897dc7951c72c912ba057d02f..d0201152611d2549512eedbce19bed12f9281d48 100644 (file)
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -522,6 +522,11 @@ class DDR4_2400_x64(DRAMCtrl):
     # constraints incurred by the bank groups
     banks_per_rank = 16
 
+    # override the default buffer sizes and go for something larger to
+    # accommodate the larger bank count
+    write_buffer_size = 128
+    read_buffer_size = 64
+
     # 1200 MHz
     tCK = '0.833ns'