mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / DRAMCtrl.py

diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index d1c5daf622754c61b3e9ee00a06d74f80b36f363..f78a7370dab849e9c05fc5ecb5391e68d6ac97c9 100644 (file)
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012-2016 ARM Limited
+# Copyright (c) 2012-2018 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -45,6 +45,7 @@
 #          Erfan Azarkhish
 
 from m5.params import *
+from m5.proxy import *
 from AbstractMemory import *
 
 # Enum for memory scheduling algorithms, currently First-Come
@@ -183,6 +184,13 @@ class DRAMCtrl(AbstractMemory):
     # for CAS-to-CAS delay for bursts to different bank groups
     tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay")
 
+    # Write-to-Write delay for bursts to the same bank group
+    # only utilized with bank group architectures; set to 0 for default case
+    # This will be used to enable different same bank group delays
+    # for writes versus reads
+    tCCD_L_WR = Param.Latency(Self.tCCD_L,
+        "Same bank group Write to Write delay")
+
     # time taken to complete one refresh cycle (N rows in all banks)
     tRFC = Param.Latency("Refresh cycle time")
 
@@ -642,6 +650,9 @@ class DDR4_2400_8x8(DDR4_2400_16x4):
     # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8)
     device_rowbuffer_size = '1kB'
 
+    # 8x8 configuration, so 8 devices
+    devices_per_rank = 8
+
     # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns)
     tRRD_L = '4.9ns';