cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / MemChecker.py

diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 7460cd13bbbc552f0e368be6c159be6d6006ef25..4a7adc8fed0f700532692a0b7a58fee1029a871a 100644 (file)
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -35,7 +35,6 @@
 #
 # Authors: Marco Elver
 
-from m5.objects.MemObject import MemObject
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
@@ -44,7 +43,7 @@ class MemChecker(SimObject):
     type = 'MemChecker'
     cxx_header = "mem/mem_checker.hh"
 
-class MemCheckerMonitor(MemObject):
+class MemCheckerMonitor(SimObject):
     type = 'MemCheckerMonitor'
     cxx_header = "mem/mem_checker_monitor.hh"