-# Copyright (c) 2005-2007 The Regents of The University of Michigan
+# Copyright (c) 2005-2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
port = VectorPort("the access port")
range = Param.AddrRange(AddrRange('128MB'), "Device Address")
file = Param.String('', "memory mapped file")
- latency = Param.Latency('1t', "latency of an access")
+ latency = Param.Latency('30ns', "latency of an access")
+ latency_var = Param.Latency('0ns', "access variablity")
zero = Param.Bool(False, "zero initialize memory")
+ null = Param.Bool(False, "do not store data, always return zero")
class DRAMMemory(PhysicalMemory):
type = 'DRAMMemory'
mem_actpolicy = Param.String("open", "Open/Close policy")
memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
bus_width = Param.Int(16, "")
- act_lat = Param.Int(2, "RAS to CAS delay")
- cas_lat = Param.Int(1, "CAS delay")
- war_lat = Param.Int(2, "write after read delay")
- pre_lat = Param.Int(2, "precharge delay")
- dpl_lat = Param.Int(2, "data in to precharge delay")
- trc_lat = Param.Int(6, "row cycle delay")
+ act_lat = Param.Latency("2ns", "RAS to CAS delay")
+ cas_lat = Param.Latency("1ns", "CAS delay")
+ war_lat = Param.Latency("2ns", "write after read delay")
+ pre_lat = Param.Latency("2ns", "precharge delay")
+ dpl_lat = Param.Latency("2ns", "data in to precharge delay")
+ trc_lat = Param.Latency("6ns", "row cycle delay")
num_banks = Param.Int(4, "Number of Banks")
num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")