Make L2+ caches allocate new block for writeback misses

[gem5.git] / src / mem / PhysicalMemory.py

diff --git a/src/mem/PhysicalMemory.py b/src/mem/PhysicalMemory.py
index 2ef3df7c1738aa7d2b2247cf213a4c44978b8bf7..99bd27f2b85c563e9581e6757008034cdf8d5328 100644 (file)
--- a/src/mem/PhysicalMemory.py
+++ b/src/mem/PhysicalMemory.py
@@ -46,12 +46,12 @@ class DRAMMemory(PhysicalMemory):
     mem_actpolicy = Param.String("open", "Open/Close policy")
     memctrladdr_type = Param.String("interleaved", "Mapping interleaved or direct")
     bus_width = Param.Int(16, "")
-    act_lat = Param.Int(2, "RAS to CAS delay")
-    cas_lat = Param.Int(1, "CAS delay")
-    war_lat = Param.Int(2, "write after read delay")
-    pre_lat = Param.Int(2, "precharge delay")
-    dpl_lat = Param.Int(2, "data in to precharge delay")
-    trc_lat = Param.Int(6, "row cycle delay")
+    act_lat = Param.Latency("2ns", "RAS to CAS delay")
+    cas_lat = Param.Latency("1ns", "CAS delay")
+    war_lat = Param.Latency("2ns", "write after read delay")
+    pre_lat = Param.Latency("2ns", "precharge delay")
+    dpl_lat = Param.Latency("2ns", "data in to precharge delay")
+    trc_lat = Param.Latency("6ns", "row cycle delay")
     num_banks = Param.Int(4, "Number of Banks")
     num_cpus = Param.Int(4, "Number of CPUs connected to DRAM")