SimObject('MemObject.py')
SimObject('PhysicalMemory.py')
-if env['RUBY']:
- SimObject('RubyMemory.py')
-
Source('bridge.cc')
Source('bus.cc')
Source('dram.cc')
Source('tport.cc')
Source('mport.cc')
-if env['RUBY']:
- Source('rubymem.cc')
-
if env['FULL_SYSTEM']:
Source('vport.cc')
else:
TraceFlag('LLSC')
TraceFlag('MMU')
TraceFlag('MemoryAccess')
+TraceFlag('Ruby')