mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 3b65131a2f05d5c8f2a8d6570d308680b89d76f5..625eb060837bfdc4befe644c46849c2ad42a0b9d 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -43,6 +43,7 @@ SimObject('MemObject.py')
 SimObject('SimpleMemory.py')
 SimObject('XBar.py')
 SimObject('HMCController.py')
+SimObject('SerialLink.py')
 
 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
@@ -66,13 +67,12 @@ Source('stack_dist_calc.cc')
 Source('tport.cc')
 Source('xbar.cc')
 Source('hmc_controller.cc')
+Source('serial_link.cc')
 
 if env['TARGET_ISA'] != 'null':
     Source('fs_translating_port_proxy.cc')
     Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
-if env['TARGET_ISA'] == 'x86':
-    Source('multi_level_page_table.cc')
 
 if env['HAVE_DRAMSIM']:
     SimObject('DRAMSim2.py')
@@ -104,6 +104,7 @@ DebugFlag('PacketQueue')
 DebugFlag('StackDist')
 DebugFlag("DRAMSim2")
 DebugFlag('HMCController')
+DebugFlag('SerialLink')
 
 DebugFlag("MemChecker")
 DebugFlag("MemCheckerMonitor")