SimObject('MemObject.py')
SimObject('SimpleMemory.py')
SimObject('XBar.py')
+SimObject('HMCController.py')
+SimObject('SerialLink.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
Source('stack_dist_calc.cc')
Source('tport.cc')
Source('xbar.cc')
+Source('hmc_controller.cc')
+Source('serial_link.cc')
if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
-if env['TARGET_ISA'] == 'x86':
- Source('multi_level_page_table.cc')
if env['HAVE_DRAMSIM']:
SimObject('DRAMSim2.py')
DebugFlag('PacketQueue')
DebugFlag('StackDist')
DebugFlag("DRAMSim2")
+DebugFlag('HMCController')
+DebugFlag('SerialLink')
DebugFlag("MemChecker")
DebugFlag("MemCheckerMonitor")