mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 6d225385bcde287966e17dadb4c3b6b0174bf532..625eb060837bfdc4befe644c46849c2ad42a0b9d 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,19 +30,20 @@
 
 Import('*')
 
-# Only build the communication if we have support for protobuf as the
-# tracing relies on it
-if env['HAVE_PROTOBUF']:
-    SimObject('CommMonitor.py')
-    Source('comm_monitor.cc')
+SimObject('CommMonitor.py')
+Source('comm_monitor.cc')
 
 SimObject('AbstractMemory.py')
 SimObject('AddrMapper.py')
 SimObject('Bridge.py')
 SimObject('DRAMCtrl.py')
+SimObject('ExternalMaster.py')
+SimObject('ExternalSlave.py')
 SimObject('MemObject.py')
 SimObject('SimpleMemory.py')
 SimObject('XBar.py')
+SimObject('HMCController.py')
+SimObject('SerialLink.py')
 
 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
@@ -50,6 +51,8 @@ Source('bridge.cc')
 Source('coherent_xbar.cc')
 Source('drampower.cc')
 Source('dram_ctrl.cc')
+Source('external_master.cc')
+Source('external_slave.cc')
 Source('mem_object.cc')
 Source('mport.cc')
 Source('noncoherent_xbar.cc')
@@ -60,21 +63,26 @@ Source('port_proxy.cc')
 Source('physical.cc')
 Source('simple_mem.cc')
 Source('snoop_filter.cc')
+Source('stack_dist_calc.cc')
 Source('tport.cc')
 Source('xbar.cc')
+Source('hmc_controller.cc')
+Source('serial_link.cc')
 
 if env['TARGET_ISA'] != 'null':
     Source('fs_translating_port_proxy.cc')
     Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
-if env['TARGET_ISA'] == 'x86':
-    Source('multi_level_page_table.cc')
 
 if env['HAVE_DRAMSIM']:
     SimObject('DRAMSim2.py')
     Source('dramsim2_wrapper.cc')
     Source('dramsim2.cc')
 
+SimObject('MemChecker.py')
+Source('mem_checker.cc')
+Source('mem_checker_monitor.cc')
+
 DebugFlag('AddrRanges')
 DebugFlag('BaseXBar')
 DebugFlag('CoherentXBar')
@@ -88,9 +96,15 @@ DebugFlag('CommMonitor')
 DebugFlag('DRAM')
 DebugFlag('DRAMPower')
 DebugFlag('DRAMState')
+DebugFlag('ExternalPort')
 DebugFlag('LLSC')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')
-
+DebugFlag('StackDist')
 DebugFlag("DRAMSim2")
+DebugFlag('HMCController')
+DebugFlag('SerialLink')
+
+DebugFlag("MemChecker")
+DebugFlag("MemCheckerMonitor")