mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index e6973b1ac66be929ce69096b2485f97de866f38f..625eb060837bfdc4befe644c46849c2ad42a0b9d 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,11 +30,8 @@
 
 Import('*')
 
-# Only build the communication if we have support for protobuf as the
-# tracing relies on it
-if env['HAVE_PROTOBUF']:
-    SimObject('CommMonitor.py')
-    Source('comm_monitor.cc')
+SimObject('CommMonitor.py')
+Source('comm_monitor.cc')
 
 SimObject('AbstractMemory.py')
 SimObject('AddrMapper.py')
@@ -45,6 +42,8 @@ SimObject('ExternalSlave.py')
 SimObject('MemObject.py')
 SimObject('SimpleMemory.py')
 SimObject('XBar.py')
+SimObject('HMCController.py')
+SimObject('SerialLink.py')
 
 Source('abstract_mem.cc')
 Source('addr_mapper.cc')
@@ -64,15 +63,16 @@ Source('port_proxy.cc')
 Source('physical.cc')
 Source('simple_mem.cc')
 Source('snoop_filter.cc')
+Source('stack_dist_calc.cc')
 Source('tport.cc')
 Source('xbar.cc')
+Source('hmc_controller.cc')
+Source('serial_link.cc')
 
 if env['TARGET_ISA'] != 'null':
     Source('fs_translating_port_proxy.cc')
     Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
-if env['TARGET_ISA'] == 'x86':
-    Source('multi_level_page_table.cc')
 
 if env['HAVE_DRAMSIM']:
     SimObject('DRAMSim2.py')
@@ -101,8 +101,10 @@ DebugFlag('LLSC')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')
-
+DebugFlag('StackDist')
 DebugFlag("DRAMSim2")
+DebugFlag('HMCController')
+DebugFlag('SerialLink')
 
 DebugFlag("MemChecker")
 DebugFlag("MemCheckerMonitor")