Import('*')
-# Only build the communication if we have support for protobuf as the
-# tracing relies on it
-if env['HAVE_PROTOBUF']:
- SimObject('CommMonitor.py')
- Source('comm_monitor.cc')
+SimObject('CommMonitor.py')
+Source('comm_monitor.cc')
SimObject('AbstractMemory.py')
SimObject('AddrMapper.py')
SimObject('MemObject.py')
SimObject('SimpleMemory.py')
SimObject('XBar.py')
+SimObject('HMCController.py')
+SimObject('SerialLink.py')
Source('abstract_mem.cc')
Source('addr_mapper.cc')
Source('physical.cc')
Source('simple_mem.cc')
Source('snoop_filter.cc')
+Source('stack_dist_calc.cc')
Source('tport.cc')
Source('xbar.cc')
+Source('hmc_controller.cc')
+Source('serial_link.cc')
if env['TARGET_ISA'] != 'null':
Source('fs_translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
-if env['TARGET_ISA'] == 'x86':
- Source('multi_level_page_table.cc')
if env['HAVE_DRAMSIM']:
SimObject('DRAMSim2.py')
Source('dramsim2_wrapper.cc')
Source('dramsim2.cc')
+SimObject('MemChecker.py')
+Source('mem_checker.cc')
+Source('mem_checker_monitor.cc')
+
DebugFlag('AddrRanges')
DebugFlag('BaseXBar')
DebugFlag('CoherentXBar')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
-
+DebugFlag('StackDist')
DebugFlag("DRAMSim2")
+DebugFlag('HMCController')
+DebugFlag('SerialLink')
+
+DebugFlag("MemChecker")
+DebugFlag("MemCheckerMonitor")