Import('*')
+SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('Bus.py')
+SimObject('CommMonitor.py')
SimObject('MemObject.py')
+Source('addr_mapper.cc')
Source('bridge.cc')
Source('bus.cc')
+Source('coherent_bus.cc')
+Source('comm_monitor.cc')
Source('mem_object.cc')
Source('mport.cc')
+Source('noncoherent_bus.cc')
Source('packet.cc')
Source('port.cc')
+Source('packet_queue.cc')
Source('tport.cc')
+Source('port_proxy.cc')
Source('fs_translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
if env['TARGET_ISA'] != 'no':
- SimObject('PhysicalMemory.py')
- Source('dram.cc')
+ SimObject('AbstractMemory.py')
+ SimObject('SimpleMemory.py')
+ SimObject('SimpleDRAM.py')
+ Source('abstract_mem.cc')
+ Source('simple_mem.cc')
Source('page_table.cc')
Source('physical.cc')
+ Source('simple_dram.cc')
-DebugFlag('Bus')
+DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
-DebugFlag('BusBridge')
+DebugFlag('CoherentBus')
+DebugFlag('NoncoherentBus')
+CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
+ 'NoncoherentBus'])
+
+DebugFlag('Bridge')
+DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMWR')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
+DebugFlag('PacketQueue')
DebugFlag('ProtocolTrace')
DebugFlag('RubyCache')
DebugFlag('RubySlicc')
DebugFlag('RubySystem')
DebugFlag('RubyTester')
+DebugFlag('RubyStats')
+DebugFlag('RubyResourceStalls')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',