Mem: Use deque instead of list for bus retries
[gem5.git] / src / mem / SConscript
index 50423fa67dd5c5e0d92b4305eb741bba797e738b..9cf8b08d1e25e27b68e6bb84e50f4d8d81629242 100644 (file)
 
 Import('*')
 
+SimObject('AddrMapper.py')
 SimObject('Bridge.py')
 SimObject('Bus.py')
+SimObject('CommMonitor.py')
 SimObject('MemObject.py')
 
+Source('addr_mapper.cc')
 Source('bridge.cc')
 Source('bus.cc')
+Source('coherent_bus.cc')
+Source('comm_monitor.cc')
 Source('mem_object.cc')
+Source('mport.cc')
+Source('noncoherent_bus.cc')
 Source('packet.cc')
 Source('port.cc')
+Source('packet_queue.cc')
 Source('tport.cc')
-Source('mport.cc')
+Source('port_proxy.cc')
+Source('fs_translating_port_proxy.cc')
+Source('se_translating_port_proxy.cc')
 
 if env['TARGET_ISA'] != 'no':
-    SimObject('PhysicalMemory.py')
-    Source('dram.cc')
-    Source('physical.cc')
-
-if env['FULL_SYSTEM']:
-    Source('vport.cc')
-elif env['TARGET_ISA'] != 'no':
+    SimObject('AbstractMemory.py')
+    SimObject('SimpleMemory.py')
+    SimObject('SimpleDRAM.py')
+    Source('abstract_mem.cc')
+    Source('simple_mem.cc')
     Source('page_table.cc')
-    Source('translating_port.cc')
+    Source('physical.cc')
+    Source('simple_dram.cc')
 
-DebugFlag('Bus')
+DebugFlag('BaseBus')
 DebugFlag('BusAddrRanges')
-DebugFlag('BusBridge')
+DebugFlag('CoherentBus')
+DebugFlag('NoncoherentBus')
+CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
+                     'NoncoherentBus'])
+
+DebugFlag('Bridge')
+DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMWR')
 DebugFlag('LLSC')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
+DebugFlag('PacketQueue')
 
 DebugFlag('ProtocolTrace')
 DebugFlag('RubyCache')
@@ -73,6 +91,8 @@ DebugFlag('RubySequencer')
 DebugFlag('RubySlicc')
 DebugFlag('RubySystem')
 DebugFlag('RubyTester')
+DebugFlag('RubyStats')
+DebugFlag('RubyResourceStalls')
 
 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
     'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',