SLICC: Remove WakeUp* import calls from ast/__init__.py

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 61fb766d6536d511cd0d91924b444acd81b4ca1d..a8c42df5a647ebbffade0e152ff336d608339034 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,17 +30,48 @@
 
 Import('*')
 
+SimObject('Bridge.py')
+SimObject('Bus.py')
+SimObject('MemObject.py')
+
 Source('bridge.cc')
 Source('bus.cc')
-Source('dram.cc')
 Source('mem_object.cc')
 Source('packet.cc')
-Source('physical.cc')
 Source('port.cc')
 Source('tport.cc')
+Source('mport.cc')
+
+if env['TARGET_ISA'] != 'no':
+    SimObject('PhysicalMemory.py')
+    Source('dram.cc')
+    Source('physical.cc')
 
 if env['FULL_SYSTEM']:
     Source('vport.cc')
-else:
+elif env['TARGET_ISA'] != 'no':
     Source('page_table.cc')
     Source('translating_port.cc')
+
+TraceFlag('Bus')
+TraceFlag('BusAddrRanges')
+TraceFlag('BusBridge')
+TraceFlag('LLSC')
+TraceFlag('MMU')
+TraceFlag('MemoryAccess')
+
+TraceFlag('ProtocolTrace')
+TraceFlag('RubyCache')
+TraceFlag('RubyDma')
+TraceFlag('RubyGenerated')
+TraceFlag('RubyMemory')
+TraceFlag('RubyNetwork')
+TraceFlag('RubyPort')
+TraceFlag('RubyQueue')
+TraceFlag('RubySlicc')
+TraceFlag('RubyStorebuffer')
+TraceFlag('RubyTester')
+
+CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
+    'RubyGenerated', 'RubySlicc', 'RubyStorebuffer', 'RubyCache', 
+    'RubyMemory', 'RubyDma', 'RubyPort'])