Import('*')
+# Only build the communication if we have support for protobuf as the
+# tracing relies on it
+if env['HAVE_PROTOBUF']:
+ SimObject('CommMonitor.py')
+ Source('comm_monitor.cc')
+
+SimObject('AddrMapper.py')
SimObject('Bridge.py')
SimObject('Bus.py')
-SimObject('CommMonitor.py')
SimObject('MemObject.py')
+Source('addr_mapper.cc')
Source('bridge.cc')
Source('bus.cc')
Source('coherent_bus.cc')
-Source('comm_monitor.cc')
Source('mem_object.cc')
Source('mport.cc')
Source('noncoherent_bus.cc')
if env['TARGET_ISA'] != 'no':
SimObject('AbstractMemory.py')
SimObject('SimpleMemory.py')
+ SimObject('SimpleDRAM.py')
Source('abstract_mem.cc')
Source('simple_mem.cc')
Source('page_table.cc')
Source('physical.cc')
+ Source('simple_dram.cc')
DebugFlag('BaseBus')
DebugFlag('BusAddrRanges')
CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
'NoncoherentBus'])
-DebugFlag('BusBridge')
+DebugFlag('Bridge')
DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMWR')
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('RubyMemory')
DebugFlag('RubyNetwork')
DebugFlag('RubyPort')
+DebugFlag('RubyPrefetcher')
DebugFlag('RubyQueue')
DebugFlag('RubySequencer')
DebugFlag('RubySlicc')
DebugFlag('RubySystem')
DebugFlag('RubyTester')
DebugFlag('RubyStats')
+DebugFlag('RubyResourceStalls')
CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
- 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace'])
+ 'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
+ 'RubyPrefetcher'])