x86: changes to apic, keyboard

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index 1961204f7222e955b00a827404c08efd799fbd04..ca89418b54ebd8d3a0bc8619ef2d58221755f608 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,15 +30,21 @@
 
 Import('*')
 
+# Only build the communication if we have support for protobuf as the
+# tracing relies on it
+if env['HAVE_PROTOBUF']:
+    SimObject('CommMonitor.py')
+    Source('comm_monitor.cc')
+
+SimObject('AddrMapper.py')
 SimObject('Bridge.py')
 SimObject('Bus.py')
-SimObject('CommMonitor.py')
 SimObject('MemObject.py')
 
+Source('addr_mapper.cc')
 Source('bridge.cc')
 Source('bus.cc')
 Source('coherent_bus.cc')
-Source('comm_monitor.cc')
 Source('mem_object.cc')
 Source('mport.cc')
 Source('noncoherent_bus.cc')
@@ -53,10 +59,12 @@ Source('se_translating_port_proxy.cc')
 if env['TARGET_ISA'] != 'no':
     SimObject('AbstractMemory.py')
     SimObject('SimpleMemory.py')
+    SimObject('SimpleDRAM.py')
     Source('abstract_mem.cc')
     Source('simple_mem.cc')
     Source('page_table.cc')
     Source('physical.cc')
+    Source('simple_dram.cc')
 
 DebugFlag('BaseBus')
 DebugFlag('BusAddrRanges')
@@ -65,8 +73,10 @@ DebugFlag('NoncoherentBus')
 CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
                      'NoncoherentBus'])
 
-DebugFlag('BusBridge')
+DebugFlag('Bridge')
 DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMWR')
 DebugFlag('LLSC')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
@@ -80,12 +90,16 @@ DebugFlag('RubyGenerated')
 DebugFlag('RubyMemory')
 DebugFlag('RubyNetwork')
 DebugFlag('RubyPort')
+DebugFlag('RubyPrefetcher')
 DebugFlag('RubyQueue')
 DebugFlag('RubySequencer')
 DebugFlag('RubySlicc')
 DebugFlag('RubySystem')
 DebugFlag('RubyTester')
+DebugFlag('RubyStats')
+DebugFlag('RubyResourceStalls')
 
 CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
     'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
-    'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace'])
+    'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
+    'RubyPrefetcher'])