# -*- mode:python -*-
#
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018-2020 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
SimObject('AbstractMemory.py')
SimObject('AddrMapper.py')
SimObject('Bridge.py')
-SimObject('DRAMCtrl.py')
+SimObject('MemCtrl.py')
+SimObject('MemInterface.py')
+SimObject('DRAMInterface.py')
+SimObject('NVMInterface.py')
SimObject('ExternalMaster.py')
SimObject('ExternalSlave.py')
SimObject('MemObject.py')
Source('bridge.cc')
Source('coherent_xbar.cc')
Source('drampower.cc')
-Source('dram_ctrl.cc')
Source('external_master.cc')
Source('external_slave.cc')
+Source('mem_ctrl.cc')
+Source('mem_interface.cc')
Source('noncoherent_xbar.cc')
Source('packet.cc')
Source('port.cc')
Source('simple_mem.cc')
Source('snoop_filter.cc')
Source('stack_dist_calc.cc')
+Source('token_port.cc')
Source('tport.cc')
Source('xbar.cc')
Source('hmc_controller.cc')
+Source('htm.cc')
Source('serial_link.cc')
Source('mem_delay.cc')
Source('dramsim2_wrapper.cc')
Source('dramsim2.cc')
+if env['HAVE_DRAMSIM3']:
+ SimObject('DRAMsim3.py')
+ Source('dramsim3_wrapper.cc')
+ Source('dramsim3.cc')
+
SimObject('MemChecker.py')
Source('mem_checker.cc')
Source('mem_checker_monitor.cc')
DebugFlag('DRAM')
DebugFlag('DRAMPower')
DebugFlag('DRAMState')
+DebugFlag('NVM')
DebugFlag('ExternalPort')
+DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
DebugFlag('LLSC')
+DebugFlag('MemCtrl')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
DebugFlag('PacketQueue')
DebugFlag('StackDist')
DebugFlag("DRAMSim2")
+DebugFlag("DRAMsim3")
DebugFlag('HMCController')
DebugFlag('SerialLink')
+DebugFlag('TokenPort')
DebugFlag("MemChecker")
DebugFlag("MemCheckerMonitor")