mem-cache: Fix setting prefetch bit

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index ca89418b54ebd8d3a0bc8619ef2d58221755f608..cf7adc8668c1e95bafd6442754a176def653e4f2 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -1,5 +1,17 @@
 # -*- mode:python -*-
-
+#
+# Copyright (c) 2018-2020 ARM Limited
+# All rights reserved
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -25,81 +37,101 @@
 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Nathan Binkert
 
 Import('*')
 
-# Only build the communication if we have support for protobuf as the
-# tracing relies on it
-if env['HAVE_PROTOBUF']:
-    SimObject('CommMonitor.py')
-    Source('comm_monitor.cc')
+SimObject('CommMonitor.py')
+Source('comm_monitor.cc')
 
+SimObject('AbstractMemory.py')
 SimObject('AddrMapper.py')
 SimObject('Bridge.py')
-SimObject('Bus.py')
+SimObject('MemCtrl.py')
+SimObject('MemInterface.py')
+SimObject('DRAMInterface.py')
+SimObject('NVMInterface.py')
+SimObject('ExternalMaster.py')
+SimObject('ExternalSlave.py')
 SimObject('MemObject.py')
+SimObject('SimpleMemory.py')
+SimObject('XBar.py')
+SimObject('HMCController.py')
+SimObject('SerialLink.py')
+SimObject('MemDelay.py')
 
+Source('abstract_mem.cc')
 Source('addr_mapper.cc')
 Source('bridge.cc')
-Source('bus.cc')
-Source('coherent_bus.cc')
-Source('mem_object.cc')
-Source('mport.cc')
-Source('noncoherent_bus.cc')
+Source('coherent_xbar.cc')
+Source('drampower.cc')
+Source('external_master.cc')
+Source('external_slave.cc')
+Source('mem_ctrl.cc')
+Source('mem_interface.cc')
+Source('noncoherent_xbar.cc')
 Source('packet.cc')
 Source('port.cc')
 Source('packet_queue.cc')
-Source('tport.cc')
 Source('port_proxy.cc')
-Source('fs_translating_port_proxy.cc')
-Source('se_translating_port_proxy.cc')
+Source('physical.cc')
+Source('simple_mem.cc')
+Source('snoop_filter.cc')
+Source('stack_dist_calc.cc')
+Source('token_port.cc')
+Source('tport.cc')
+Source('xbar.cc')
+Source('hmc_controller.cc')
+Source('htm.cc')
+Source('serial_link.cc')
+Source('mem_delay.cc')
 
-if env['TARGET_ISA'] != 'no':
-    SimObject('AbstractMemory.py')
-    SimObject('SimpleMemory.py')
-    SimObject('SimpleDRAM.py')
-    Source('abstract_mem.cc')
-    Source('simple_mem.cc')
+if env['TARGET_ISA'] != 'null':
+    Source('translating_port_proxy.cc')
+    Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
-    Source('physical.cc')
-    Source('simple_dram.cc')
 
-DebugFlag('BaseBus')
-DebugFlag('BusAddrRanges')
-DebugFlag('CoherentBus')
-DebugFlag('NoncoherentBus')
-CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
-                     'NoncoherentBus'])
+if env['HAVE_DRAMSIM']:
+    SimObject('DRAMSim2.py')
+    Source('dramsim2_wrapper.cc')
+    Source('dramsim2.cc')
+
+if env['HAVE_DRAMSIM3']:
+    SimObject('DRAMsim3.py')
+    Source('dramsim3_wrapper.cc')
+    Source('dramsim3.cc')
+
+SimObject('MemChecker.py')
+Source('mem_checker.cc')
+Source('mem_checker_monitor.cc')
+
+DebugFlag('AddrRanges')
+DebugFlag('BaseXBar')
+DebugFlag('CoherentXBar')
+DebugFlag('NoncoherentXBar')
+DebugFlag('SnoopFilter')
+CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
+                      'SnoopFilter'])
 
 DebugFlag('Bridge')
 DebugFlag('CommMonitor')
 DebugFlag('DRAM')
-DebugFlag('DRAMWR')
+DebugFlag('DRAMPower')
+DebugFlag('DRAMState')
+DebugFlag('NVM')
+DebugFlag('ExternalPort')
+DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
 DebugFlag('LLSC')
+DebugFlag('MemCtrl')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')
+DebugFlag('StackDist')
+DebugFlag("DRAMSim2")
+DebugFlag("DRAMsim3")
+DebugFlag('HMCController')
+DebugFlag('SerialLink')
+DebugFlag('TokenPort')
 
-DebugFlag('ProtocolTrace')
-DebugFlag('RubyCache')
-DebugFlag('RubyCacheTrace')
-DebugFlag('RubyDma')
-DebugFlag('RubyGenerated')
-DebugFlag('RubyMemory')
-DebugFlag('RubyNetwork')
-DebugFlag('RubyPort')
-DebugFlag('RubyPrefetcher')
-DebugFlag('RubyQueue')
-DebugFlag('RubySequencer')
-DebugFlag('RubySlicc')
-DebugFlag('RubySystem')
-DebugFlag('RubyTester')
-DebugFlag('RubyStats')
-DebugFlag('RubyResourceStalls')
-
-CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
-    'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
-    'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace',
-    'RubyPrefetcher'])
+DebugFlag("MemChecker")
+DebugFlag("MemCheckerMonitor")
+DebugFlag("QOS")