mem-cache: Fix setting prefetch bit

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index d4eb4615b3a1b8fe6de588cd04e29540a97d7277..cf7adc8668c1e95bafd6442754a176def653e4f2 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 #
-# Copyright (c) 2018 ARM Limited
+# Copyright (c) 2018-2020 ARM Limited
 # All rights reserved
 #
 # The license below extends only to copyright in the software and shall
@@ -46,7 +46,10 @@ Source('comm_monitor.cc')
 SimObject('AbstractMemory.py')
 SimObject('AddrMapper.py')
 SimObject('Bridge.py')
-SimObject('DRAMCtrl.py')
+SimObject('MemCtrl.py')
+SimObject('MemInterface.py')
+SimObject('DRAMInterface.py')
+SimObject('NVMInterface.py')
 SimObject('ExternalMaster.py')
 SimObject('ExternalSlave.py')
 SimObject('MemObject.py')
@@ -61,27 +64,29 @@ Source('addr_mapper.cc')
 Source('bridge.cc')
 Source('coherent_xbar.cc')
 Source('drampower.cc')
-Source('dram_ctrl.cc')
 Source('external_master.cc')
 Source('external_slave.cc')
+Source('mem_ctrl.cc')
+Source('mem_interface.cc')
 Source('noncoherent_xbar.cc')
 Source('packet.cc')
 Source('port.cc')
 Source('packet_queue.cc')
 Source('port_proxy.cc')
 Source('physical.cc')
-Source('secure_port_proxy.cc')
 Source('simple_mem.cc')
 Source('snoop_filter.cc')
 Source('stack_dist_calc.cc')
+Source('token_port.cc')
 Source('tport.cc')
 Source('xbar.cc')
 Source('hmc_controller.cc')
+Source('htm.cc')
 Source('serial_link.cc')
 Source('mem_delay.cc')
 
 if env['TARGET_ISA'] != 'null':
-    Source('fs_translating_port_proxy.cc')
+    Source('translating_port_proxy.cc')
     Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
 
@@ -90,6 +95,11 @@ if env['HAVE_DRAMSIM']:
     Source('dramsim2_wrapper.cc')
     Source('dramsim2.cc')
 
+if env['HAVE_DRAMSIM3']:
+    SimObject('DRAMsim3.py')
+    Source('dramsim3_wrapper.cc')
+    Source('dramsim3.cc')
+
 SimObject('MemChecker.py')
 Source('mem_checker.cc')
 Source('mem_checker_monitor.cc')
@@ -107,15 +117,20 @@ DebugFlag('CommMonitor')
 DebugFlag('DRAM')
 DebugFlag('DRAMPower')
 DebugFlag('DRAMState')
+DebugFlag('NVM')
 DebugFlag('ExternalPort')
+DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
 DebugFlag('LLSC')
+DebugFlag('MemCtrl')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')
 DebugFlag('StackDist')
 DebugFlag("DRAMSim2")
+DebugFlag("DRAMsim3")
 DebugFlag('HMCController')
 DebugFlag('SerialLink')
+DebugFlag('TokenPort')
 
 DebugFlag("MemChecker")
 DebugFlag("MemCheckerMonitor")