mem: Multi Level Page Table bug fix

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index c181c88c6735573022b5872b3c9291623eb72371..e7d2c1bac25662306cee28f5cd90aff3a2dc49da 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,34 +30,72 @@
 
 Import('*')
 
+# Only build the communication if we have support for protobuf as the
+# tracing relies on it
+if env['HAVE_PROTOBUF']:
+    SimObject('CommMonitor.py')
+    Source('comm_monitor.cc')
+
+SimObject('AbstractMemory.py')
+SimObject('AddrMapper.py')
 SimObject('Bridge.py')
-SimObject('Bus.py')
-SimObject('PhysicalMemory.py')
+SimObject('DRAMCtrl.py')
+SimObject('ExternalMaster.py')
+SimObject('ExternalSlave.py')
 SimObject('MemObject.py')
+SimObject('SimpleMemory.py')
+SimObject('XBar.py')
 
-# Workaround for bug in SCons version > 0.97d20071212
-# Scons bug id: 2006 M5 Bug id: 308
-Dir('config')
-
+Source('abstract_mem.cc')
+Source('addr_mapper.cc')
 Source('bridge.cc')
-Source('bus.cc')
-Source('dram.cc')
+Source('coherent_xbar.cc')
+Source('drampower.cc')
+Source('dram_ctrl.cc')
+Source('external_master.cc')
+Source('external_slave.cc')
 Source('mem_object.cc')
+Source('mport.cc')
+Source('noncoherent_xbar.cc')
 Source('packet.cc')
-Source('physical.cc')
 Source('port.cc')
+Source('packet_queue.cc')
+Source('port_proxy.cc')
+Source('physical.cc')
+Source('simple_mem.cc')
+Source('snoop_filter.cc')
 Source('tport.cc')
-Source('mport.cc')
+Source('xbar.cc')
 
-if env['FULL_SYSTEM']:
-    Source('vport.cc')
-else:
+if env['TARGET_ISA'] != 'null':
+    Source('fs_translating_port_proxy.cc')
+    Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
-    Source('translating_port.cc')
-
-TraceFlag('Bus')
-TraceFlag('BusAddrRanges')
-TraceFlag('BusBridge')
-TraceFlag('LLSC')
-TraceFlag('MMU')
-TraceFlag('MemoryAccess')
+if env['TARGET_ISA'] == 'x86':
+    Source('multi_level_page_table.cc')
+
+if env['HAVE_DRAMSIM']:
+    SimObject('DRAMSim2.py')
+    Source('dramsim2_wrapper.cc')
+    Source('dramsim2.cc')
+
+DebugFlag('AddrRanges')
+DebugFlag('BaseXBar')
+DebugFlag('CoherentXBar')
+DebugFlag('NoncoherentXBar')
+DebugFlag('SnoopFilter')
+CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
+                      'SnoopFilter'])
+
+DebugFlag('Bridge')
+DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMPower')
+DebugFlag('DRAMState')
+DebugFlag('ExternalPort')
+DebugFlag('LLSC')
+DebugFlag('MMU')
+DebugFlag('MemoryAccess')
+DebugFlag('PacketQueue')
+
+DebugFlag("DRAMSim2")