mem: Multi Level Page Table bug fix

[gem5.git] / src / mem / SConscript

diff --git a/src/mem/SConscript b/src/mem/SConscript
index d290da8752af8281f8d578b3d7a9aa4bab6fe758..e7d2c1bac25662306cee28f5cd90aff3a2dc49da 100644 (file)
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -30,64 +30,72 @@
 
 Import('*')
 
+# Only build the communication if we have support for protobuf as the
+# tracing relies on it
+if env['HAVE_PROTOBUF']:
+    SimObject('CommMonitor.py')
+    Source('comm_monitor.cc')
+
+SimObject('AbstractMemory.py')
+SimObject('AddrMapper.py')
 SimObject('Bridge.py')
-SimObject('Bus.py')
-SimObject('CommMonitor.py')
+SimObject('DRAMCtrl.py')
+SimObject('ExternalMaster.py')
+SimObject('ExternalSlave.py')
 SimObject('MemObject.py')
+SimObject('SimpleMemory.py')
+SimObject('XBar.py')
 
+Source('abstract_mem.cc')
+Source('addr_mapper.cc')
 Source('bridge.cc')
-Source('bus.cc')
-Source('coherent_bus.cc')
-Source('comm_monitor.cc')
+Source('coherent_xbar.cc')
+Source('drampower.cc')
+Source('dram_ctrl.cc')
+Source('external_master.cc')
+Source('external_slave.cc')
 Source('mem_object.cc')
 Source('mport.cc')
-Source('noncoherent_bus.cc')
+Source('noncoherent_xbar.cc')
 Source('packet.cc')
 Source('port.cc')
 Source('packet_queue.cc')
-Source('tport.cc')
 Source('port_proxy.cc')
-Source('fs_translating_port_proxy.cc')
-Source('se_translating_port_proxy.cc')
+Source('physical.cc')
+Source('simple_mem.cc')
+Source('snoop_filter.cc')
+Source('tport.cc')
+Source('xbar.cc')
 
-if env['TARGET_ISA'] != 'no':
-    SimObject('AbstractMemory.py')
-    SimObject('SimpleMemory.py')
-    Source('abstract_mem.cc')
-    Source('simple_mem.cc')
+if env['TARGET_ISA'] != 'null':
+    Source('fs_translating_port_proxy.cc')
+    Source('se_translating_port_proxy.cc')
     Source('page_table.cc')
-    Source('physical.cc')
+if env['TARGET_ISA'] == 'x86':
+    Source('multi_level_page_table.cc')
 
-DebugFlag('BaseBus')
-DebugFlag('BusAddrRanges')
-DebugFlag('CoherentBus')
-DebugFlag('NoncoherentBus')
-CompoundFlag('Bus', ['BaseBus', 'BusAddrRanges', 'CoherentBus',
-                     'NoncoherentBus'])
+if env['HAVE_DRAMSIM']:
+    SimObject('DRAMSim2.py')
+    Source('dramsim2_wrapper.cc')
+    Source('dramsim2.cc')
 
-DebugFlag('BusBridge')
+DebugFlag('AddrRanges')
+DebugFlag('BaseXBar')
+DebugFlag('CoherentXBar')
+DebugFlag('NoncoherentXBar')
+DebugFlag('SnoopFilter')
+CompoundFlag('XBar', ['BaseXBar', 'CoherentXBar', 'NoncoherentXBar',
+                      'SnoopFilter'])
+
+DebugFlag('Bridge')
 DebugFlag('CommMonitor')
+DebugFlag('DRAM')
+DebugFlag('DRAMPower')
+DebugFlag('DRAMState')
+DebugFlag('ExternalPort')
 DebugFlag('LLSC')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')
 
-DebugFlag('ProtocolTrace')
-DebugFlag('RubyCache')
-DebugFlag('RubyCacheTrace')
-DebugFlag('RubyDma')
-DebugFlag('RubyGenerated')
-DebugFlag('RubyMemory')
-DebugFlag('RubyNetwork')
-DebugFlag('RubyPort')
-DebugFlag('RubyQueue')
-DebugFlag('RubySequencer')
-DebugFlag('RubySlicc')
-DebugFlag('RubySystem')
-DebugFlag('RubyTester')
-DebugFlag('RubyStats')
-DebugFlag('RubyResourceStalls')
-
-CompoundFlag('Ruby', [ 'RubyQueue', 'RubyNetwork', 'RubyTester',
-    'RubyGenerated', 'RubySlicc', 'RubySystem', 'RubyCache',
-    'RubyMemory', 'RubyDma', 'RubyPort', 'RubySequencer', 'RubyCacheTrace'])
+DebugFlag("DRAMSim2")