mem-cache: Fix setting prefetch bit

[gem5.git] / src / mem / SerialLink.py

diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index 254c623ebe965e1a05585fe53af1b43546285d70..7cde69fc6f5e8fbe17b074b3c5ec57b3ad2ca29a 100644 (file)
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -46,8 +46,14 @@ from m5.objects.ClockedObject import ClockedObject
 class SerialLink(ClockedObject):
     type = 'SerialLink'
     cxx_header = "mem/serial_link.hh"
-    slave = SlavePort('Slave port')
-    master = MasterPort('Master port')
+    mem_side_port = RequestPort("This port sends requests and "
+                                            "receives responses")
+    master   = DeprecatedParam(mem_side_port,
+                                '`master` is now called `mem_side_port`')
+    cpu_side_port = ResponsePort("This port receives requests and "
+                                                    "sends responses")
+    slave    = DeprecatedParam(cpu_side_port,
+                                '`slave` is now called `cpu_side_port`')
     req_size = Param.Unsigned(16, "The number of requests to buffer")
     resp_size = Param.Unsigned(16, "The number of responses to buffer")
     delay = Param.Latency('0ns', "The latency of this serial_link")