ruby: MI protocol: add a missing transition

[gem5.git] / src / mem / SimpleMemory.py

diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 51de3374d7206b99cf1cdd5bffe8c7f4b3d91c1d..0cf6dece3c9407e6a99bf45b65ae3934b811dc5d 100644 (file)
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -44,6 +44,11 @@ from AbstractMemory import *
 
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'
-    port = VectorSlavePort("Slave ports")
+    cxx_header = "mem/simple_mem.hh"
+    port = SlavePort("Slave ports")
     latency = Param.Latency('30ns', "Request to response latency")
     latency_var = Param.Latency('0ns', "Request to response latency variance")
+    # The memory bandwidth limit default is set to 12.8GB/s which is
+    # representative of a x64 DDR3-1600 channel.
+    bandwidth = Param.MemoryBandwidth('12.8GB/s',
+                                      "Combined read and write bandwidth")