ruby: MI protocol: add a missing transition

[gem5.git] / src / mem / SimpleMemory.py

diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 9361b45d8caf5cd1734ffbaf5d2a167484e3f949..0cf6dece3c9407e6a99bf45b65ae3934b811dc5d 100644 (file)
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -44,6 +44,7 @@ from AbstractMemory import *
 
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'
+    cxx_header = "mem/simple_mem.hh"
     port = SlavePort("Slave ports")
     latency = Param.Latency('30ns', "Request to response latency")
     latency_var = Param.Latency('0ns', "Request to response latency variance")