class SimpleMemory(AbstractMemory):
type = 'SimpleMemory'
- port = VectorSlavePort("Slave ports")
+ cxx_header = "mem/simple_mem.hh"
+ port = SlavePort("Slave ports")
latency = Param.Latency('30ns', "Request to response latency")
latency_var = Param.Latency('0ns', "Request to response latency variance")
+ # The memory bandwidth limit default is set to 12.8GB/s which is
+ # representative of a x64 DDR3-1600 channel.
+ bandwidth = Param.MemoryBandwidth('12.8GB/s',
+ "Combined read and write bandwidth")