mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / XBar.py

diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index a445b5e37ec45c7e8c2223d4b2baaae1d233af97..655d9808a2c0910d911dcfdc87845fd2c37afeac 100644 (file)
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2012, 2015 ARM Limited
+# Copyright (c) 2012, 2015, 2017 ARM Limited
 # All rights reserved.
 #
 # The license below extends only to copyright in the software and shall
@@ -100,6 +100,16 @@ class CoherentXBar(BaseXBar):
     # An optional snoop filter
     snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter")
 
+    # Determine how this crossbar handles packets where caches have
+    # already committed to responding, by establishing if the crossbar
+    # is the point of coherency or not.
+    point_of_coherency = Param.Bool(False, "Consider this crossbar the " \
+                                    "point of coherency")
+
+    # Specify whether this crossbar is the point of unification.
+    point_of_unification = Param.Bool(False, "Consider this crossbar the " \
+                                      "point of unification")
+
     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 
 class SnoopFilter(SimObject):
@@ -112,6 +122,9 @@ class SnoopFilter(SimObject):
 
     system = Param.System(Parent.any, "System that the crossbar belongs to.")
 
+    # Sanity check on max capacity to track, adjust if needed.
+    max_capacity = Param.MemorySize('8MB', "Maximum capacity of snoop filter")
+
 # We use a coherent crossbar to connect multiple masters to the L2
 # caches. Normally this crossbar would be part of the cache itself.
 class L2XBar(CoherentXBar):
@@ -125,6 +138,16 @@ class L2XBar(CoherentXBar):
     response_latency = 1
     snoop_response_latency = 1
 
+    # Use a snoop-filter by default, and set the latency to zero as
+    # the lookup is assumed to overlap with the frontend latency of
+    # the crossbar
+    snoop_filter = SnoopFilter(lookup_latency = 0)
+
+    # This specialisation of the coherent crossbar is to be considered
+    # the point of unification, it connects the dcache and the icache
+    # to the first level of unified cache.
+    point_of_unification = True
+
 # One of the key coherent crossbar instances is the system
 # interconnect, tying together the CPU clusters, GPUs, and any I/O
 # coherent masters, and DRAM controllers.
@@ -139,6 +162,21 @@ class SystemXBar(CoherentXBar):
     response_latency = 2
     snoop_response_latency = 4
 
+    # Use a snoop-filter by default
+    snoop_filter = SnoopFilter(lookup_latency = 1)
+
+    # This specialisation of the coherent crossbar is to be considered
+    # the point of coherency, as there are no (coherent) downstream
+    # caches.
+    point_of_coherency = True
+
+    # This specialisation of the coherent crossbar is to be considered
+    # the point of unification, it connects the dcache and the icache
+    # to the first level of unified cache. This is needed for systems
+    # without caches where the SystemXBar is also the point of
+    # unification.
+    point_of_unification = True
+
 # In addition to the system interconnect, we typically also have one
 # or more on-chip I/O crossbars. Note that at some point we might want
 # to also define an off-chip I/O crossbar such as PCIe.