AbstractMemory::AbstractMemory(const Params *p) :
MemObject(p), range(params()->range), pmemAddr(NULL),
+ backdoor(params()->range, nullptr,
+ (MemBackdoor::Flags)(MemBackdoor::Readable |
+ MemBackdoor::Writeable)),
confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
kvmMap(p->kvm_map), _system(NULL)
{
void
AbstractMemory::setBackingStore(uint8_t* pmem_addr)
{
+ // If there was an existing backdoor, let everybody know it's going away.
+ if (backdoor.ptr())
+ backdoor.invalidate();
+
+ // The back door can't handle interleaved memory.
+ backdoor.ptr(range.interleaved() ? nullptr : pmem_addr);
+
pmemAddr = pmem_addr;
}
void
AbstractMemory::trackLoadLocked(PacketPtr pkt)
{
- Request *req = pkt->req;
+ const RequestPtr &req = pkt->req;
Addr paddr = LockedAddr::mask(req->getPaddr());
// first we check if we already have a locked addr for this
bool
AbstractMemory::checkLockedAddrList(PacketPtr pkt)
{
- Request *req = pkt->req;
+ const RequestPtr &req = pkt->req;
Addr paddr = LockedAddr::mask(req->getPaddr());
bool isLLSC = pkt->isLLSC();
return allowStore;
}
-
#if TRACING_ON
+static inline void
+tracePacket(System *sys, const char *label, PacketPtr pkt)
+{
+ int size = pkt->getSize();
+#if THE_ISA != NULL_ISA
+ if (size == 1 || size == 2 || size == 4 || size == 8) {
+ DPRINTF(MemoryAccess,"%s from %s of size %i on address %#x data "
+ "%#x %c\n", label, sys->getMasterName(pkt->req->masterId()),
+ size, pkt->getAddr(), pkt->getUintX(TheISA::GuestByteOrder),
+ pkt->req->isUncacheable() ? 'U' : 'C');
+ return;
+ }
+#endif
+ DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
+ label, sys->getMasterName(pkt->req->masterId()),
+ size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
+ DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
+}
-#define CASE(A, T) \
- case sizeof(T): \
- DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \
- "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\
- pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \
- pkt->req->isUncacheable() ? 'U' : 'C'); \
- break
-
-
-#define TRACE_PACKET(A) \
- do { \
- switch (pkt->getSize()) { \
- CASE(A, uint64_t); \
- CASE(A, uint32_t); \
- CASE(A, uint16_t); \
- CASE(A, uint8_t); \
- default: \
- DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\
- A, system()->getMasterName(pkt->req->masterId()), \
- pkt->getSize(), pkt->getAddr(), \
- pkt->req->isUncacheable() ? 'U' : 'C'); \
- DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize()); \
- } \
- } while (0)
-
+# define TRACE_PACKET(A) tracePacket(system(), A, pkt)
#else
-
-#define TRACE_PACKET(A)
-
+# define TRACE_PACKET(A)
#endif
void
return;
}
- assert(AddrRange(pkt->getAddr(),
- pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range));
+ assert(pkt->getAddrRange().isSubset(range));
uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
if (pkt->cmd == MemCmd::SwapReq) {
if (pkt->isAtomicOp()) {
if (pmemAddr) {
- memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
+ pkt->setData(hostAddr);
(*(pkt->getAtomicOp()))(hostAddr);
}
} else {
uint64_t condition_val64;
uint32_t condition_val32;
- if (!pmemAddr)
- panic("Swap only works if there is real memory (i.e. null=False)");
+ panic_if(!pmemAddr, "Swap only works if there is real memory " \
+ "(i.e. null=False)");
bool overwrite_mem = true;
// keep a copy of our possible write value, and copy what is at the
// memory address into the packet
- std::memcpy(&overwrite_val[0], pkt->getConstPtr<uint8_t>(),
- pkt->getSize());
- std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
+ pkt->writeData(&overwrite_val[0]);
+ pkt->setData(hostAddr);
if (pkt->req->isCondSwap()) {
if (pkt->getSize() == sizeof(uint64_t)) {
// to do the LL/SC tracking here
trackLoadLocked(pkt);
}
- if (pmemAddr)
- memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
+ if (pmemAddr) {
+ pkt->setData(hostAddr);
+ }
TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
numReads[pkt->req->masterId()]++;
bytesRead[pkt->req->masterId()] += pkt->getSize();
if (pkt->req->isInstFetch())
bytesInstRead[pkt->req->masterId()] += pkt->getSize();
- } else if (pkt->isInvalidate()) {
+ } else if (pkt->isInvalidate() || pkt->isClean()) {
+ assert(!pkt->isWrite());
+ // in a fastmem system invalidating and/or cleaning packets
+ // can be seen due to cache maintenance requests
+
// no need to do anything
- // this clause is intentionally before the write clause: the only
- // transaction that is both a write and an invalidate is
- // WriteInvalidate, and for the sake of consistency, it does not
- // write to memory. in a cacheless system, there are no WriteInv's
- // because the Write -> WriteInvalidate rewrite happens in the cache.
} else if (pkt->isWrite()) {
if (writeOK(pkt)) {
if (pmemAddr) {
- memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
+ pkt->writeData(hostAddr);
DPRINTF(MemoryAccess, "%s wrote %i bytes to address %x\n",
__func__, pkt->getSize(), pkt->getAddr());
}
bytesWritten[pkt->req->masterId()] += pkt->getSize();
}
} else {
- panic("unimplemented");
+ panic("Unexpected packet %s", pkt->print());
}
if (pkt->needsResponse()) {
void
AbstractMemory::functionalAccess(PacketPtr pkt)
{
- assert(AddrRange(pkt->getAddr(),
- pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
+ assert(pkt->getAddrRange().isSubset(range));
uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
if (pkt->isRead()) {
- if (pmemAddr)
- memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
+ if (pmemAddr) {
+ pkt->setData(hostAddr);
+ }
TRACE_PACKET("Read");
pkt->makeResponse();
} else if (pkt->isWrite()) {
- if (pmemAddr)
- memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
+ if (pmemAddr) {
+ pkt->writeData(hostAddr);
+ }
TRACE_PACKET("Write");
pkt->makeResponse();
} else if (pkt->isPrint()) {
projects / gem5.git / blobdiff