ruby: handle llsc accesses through CacheEntry, not CacheMemory

[gem5.git] / src / mem / abstract_mem.cc

diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index c819ce2fc0edc055f21e3d301eb86439ada7f711..4690a5d8091fb2f5e42808e7fcf6424b35356496 100644 (file)
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -309,7 +309,7 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt)
                     A, system()->getMasterName(pkt->req->masterId()),          \
                     pkt->getSize(), pkt->getAddr(),                            \
                     pkt->req->isUncacheable() ? 'U' : 'C');                    \
-            DDUMP(MemoryAccess, pkt->getPtr<uint8_t>(), pkt->getSize());       \
+            DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());  \
         }                                                                      \
     } while (0)
 
@@ -322,15 +322,21 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt)
 void
 AbstractMemory::access(PacketPtr pkt)
 {
-    assert(AddrRange(pkt->getAddr(),
-                     pkt->getAddr() + pkt->getSize() - 1).isSubset(range));
-
     if (pkt->memInhibitAsserted()) {
         DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
                 pkt->getAddr());
         return;
     }
 
+    if (pkt->cmd == MemCmd::CleanEvict) {
+        DPRINTF(MemoryAccess, "CleanEvict  on 0x%x: not responding\n",
+                pkt->getAddr());
+      return;
+    }
+
+    assert(AddrRange(pkt->getAddr(),
+                     pkt->getAddr() + (pkt->getSize() - 1)).isSubset(range));
+
     uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
 
     if (pkt->cmd == MemCmd::SwapReq) {
@@ -344,7 +350,8 @@ AbstractMemory::access(PacketPtr pkt)
         bool overwrite_mem = true;
         // keep a copy of our possible write value, and copy what is at the
         // memory address into the packet
-        std::memcpy(&overwrite_val[0], pkt->getPtr<uint8_t>(), pkt->getSize());
+        std::memcpy(&overwrite_val[0], pkt->getConstPtr<uint8_t>(),
+                    pkt->getSize());
         std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
 
         if (pkt->req->isCondSwap()) {
@@ -378,10 +385,17 @@ AbstractMemory::access(PacketPtr pkt)
         bytesRead[pkt->req->masterId()] += pkt->getSize();
         if (pkt->req->isInstFetch())
             bytesInstRead[pkt->req->masterId()] += pkt->getSize();
+    } else if (pkt->isInvalidate()) {
+        // no need to do anything
+        // this clause is intentionally before the write clause: the only
+        // transaction that is both a write and an invalidate is
+        // WriteInvalidate, and for the sake of consistency, it does not
+        // write to memory.  in a cacheless system, there are no WriteInv's
+        // because the Write -> WriteInvalidate rewrite happens in the cache.
     } else if (pkt->isWrite()) {
         if (writeOK(pkt)) {
             if (pmemAddr) {
-                memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
+                memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
                 DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n",
                         __func__, pkt->getSize(), pkt->getAddr());
             }
@@ -390,8 +404,6 @@ AbstractMemory::access(PacketPtr pkt)
             numWrites[pkt->req->masterId()]++;
             bytesWritten[pkt->req->masterId()] += pkt->getSize();
         }
-    } else if (pkt->isInvalidate()) {
-        // no need to do anything
     } else {
         panic("unimplemented");
     }
@@ -416,7 +428,7 @@ AbstractMemory::functionalAccess(PacketPtr pkt)
         pkt->makeResponse();
     } else if (pkt->isWrite()) {
         if (pmemAddr)
-            memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
+            memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
         TRACE_PACKET("Write");
         pkt->makeResponse();
     } else if (pkt->isPrint()) {