/*
- * Copyright (c) 2010-2012,2017 ARM Limited
+ * Copyright (c) 2010-2012,2017-2019 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ron Dreslinski
- * Ali Saidi
- * Andreas Hansson
*/
#include "mem/abstract_mem.hh"
#include <vector>
#include "arch/locked_mem.hh"
-#include "cpu/base.hh"
+#include "base/loader/memory_image.hh"
+#include "base/loader/object_file.hh"
#include "cpu/thread_context.hh"
#include "debug/LLSC.hh"
#include "debug/MemoryAccess.hh"
#include "mem/packet_access.hh"
#include "sim/system.hh"
-using namespace std;
-
-AbstractMemory::AbstractMemory(const Params *p) :
- MemObject(p), range(params()->range), pmemAddr(NULL),
- backdoor(params()->range, nullptr,
+AbstractMemory::AbstractMemory(const Params &p) :
+ ClockedObject(p), range(p.range), pmemAddr(NULL),
+ backdoor(params().range, nullptr,
(MemBackdoor::Flags)(MemBackdoor::Readable |
MemBackdoor::Writeable)),
- confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
- kvmMap(p->kvm_map), _system(NULL)
+ confTableReported(p.conf_table_reported), inAddrMap(p.in_addr_map),
+ kvmMap(p.kvm_map), _system(NULL),
+ stats(*this)
{
+ panic_if(!range.valid() || !range.size(),
+ "Memory range %s must be valid with non-zero size.",
+ range.to_string());
}
void
-AbstractMemory::init()
+AbstractMemory::initState()
{
- assert(system());
+ ClockedObject::initState();
+
+ const auto &file = params().image_file;
+ if (file == "")
+ return;
+
+ auto *object = Loader::createObjectFile(file, true);
+ fatal_if(!object, "%s: Could not load %s.", name(), file);
+
+ Loader::debugSymbolTable.insert(*object->symtab().globals());
+ Loader::MemoryImage image = object->buildImage();
- if (size() % _system->getPageBytes() != 0)
- panic("Memory Size not divisible by page size\n");
+ AddrRange image_range(image.minAddr(), image.maxAddr());
+ if (!range.contains(image_range.start())) {
+ warn("%s: Moving image from %s to memory address range %s.",
+ name(), image_range.to_string(), range.to_string());
+ image = image.offset(range.start());
+ image_range = AddrRange(image.minAddr(), image.maxAddr());
+ }
+ panic_if(!image_range.isSubset(range), "%s: memory image %s doesn't fit.",
+ name(), file);
+
+ PortProxy proxy([this](PacketPtr pkt) { functionalAccess(pkt); },
+ system()->cacheLineSize());
+
+ panic_if(!image.write(proxy), "%s: Unable to write image.");
}
void
pmemAddr = pmem_addr;
}
-void
-AbstractMemory::regStats()
+AbstractMemory::MemStats::MemStats(AbstractMemory &_mem)
+ : Stats::Group(&_mem), mem(_mem),
+ ADD_STAT(bytesRead, UNIT_BYTE, "Number of bytes read from this memory"),
+ ADD_STAT(bytesInstRead, UNIT_BYTE,
+ "Number of instructions bytes read from this memory"),
+ ADD_STAT(bytesWritten, UNIT_BYTE,
+ "Number of bytes written to this memory"),
+ ADD_STAT(numReads, UNIT_COUNT,
+ "Number of read requests responded to by this memory"),
+ ADD_STAT(numWrites, UNIT_COUNT,
+ "Number of write requests responded to by this memory"),
+ ADD_STAT(numOther, UNIT_COUNT,
+ "Number of other requests responded to by this memory"),
+ ADD_STAT(bwRead, UNIT_RATE(Stats::Units::Byte, Stats::Units::Second),
+ "Total read bandwidth from this memory"),
+ ADD_STAT(bwInstRead, UNIT_RATE(Stats::Units::Byte, Stats::Units::Second),
+ "Instruction read bandwidth from this memory"),
+ ADD_STAT(bwWrite, UNIT_RATE(Stats::Units::Byte, Stats::Units::Second),
+ "Write bandwidth from this memory"),
+ ADD_STAT(bwTotal, UNIT_RATE(Stats::Units::Byte, Stats::Units::Second),
+ "Total bandwidth to/from this memory")
{
- MemObject::regStats();
+}
+void
+AbstractMemory::MemStats::regStats()
+{
using namespace Stats;
- assert(system());
+ Stats::Group::regStats();
+
+ System *sys = mem.system();
+ assert(sys);
+ const auto max_requestors = sys->maxRequestors();
bytesRead
- .init(system()->maxMasters())
- .name(name() + ".bytes_read")
- .desc("Number of bytes read from this memory")
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- bytesRead.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ bytesRead.subname(i, sys->getRequestorName(i));
}
+
bytesInstRead
- .init(system()->maxMasters())
- .name(name() + ".bytes_inst_read")
- .desc("Number of instructions bytes read from this memory")
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- bytesInstRead.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ bytesInstRead.subname(i, sys->getRequestorName(i));
}
+
bytesWritten
- .init(system()->maxMasters())
- .name(name() + ".bytes_written")
- .desc("Number of bytes written to this memory")
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- bytesWritten.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ bytesWritten.subname(i, sys->getRequestorName(i));
}
+
numReads
- .init(system()->maxMasters())
- .name(name() + ".num_reads")
- .desc("Number of read requests responded to by this memory")
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- numReads.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ numReads.subname(i, sys->getRequestorName(i));
}
+
numWrites
- .init(system()->maxMasters())
- .name(name() + ".num_writes")
- .desc("Number of write requests responded to by this memory")
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- numWrites.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ numWrites.subname(i, sys->getRequestorName(i));
}
+
numOther
- .init(system()->maxMasters())
- .name(name() + ".num_other")
- .desc("Number of other requests responded to by this memory")
+ .init(max_requestors)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- numOther.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ numOther.subname(i, sys->getRequestorName(i));
}
+
bwRead
- .name(name() + ".bw_read")
- .desc("Total read bandwidth from this memory (bytes/s)")
.precision(0)
.prereq(bytesRead)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- bwRead.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ bwRead.subname(i, sys->getRequestorName(i));
}
bwInstRead
- .name(name() + ".bw_inst_read")
- .desc("Instruction read bandwidth from this memory (bytes/s)")
.precision(0)
.prereq(bytesInstRead)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- bwInstRead.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ bwInstRead.subname(i, sys->getRequestorName(i));
}
+
bwWrite
- .name(name() + ".bw_write")
- .desc("Write bandwidth from this memory (bytes/s)")
.precision(0)
.prereq(bytesWritten)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- bwWrite.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ bwWrite.subname(i, sys->getRequestorName(i));
}
+
bwTotal
- .name(name() + ".bw_total")
- .desc("Total bandwidth to/from this memory (bytes/s)")
.precision(0)
.prereq(bwTotal)
.flags(total | nozero | nonan)
;
- for (int i = 0; i < system()->maxMasters(); i++) {
- bwTotal.subname(i, system()->getMasterName(i));
+ for (int i = 0; i < max_requestors; i++) {
+ bwTotal.subname(i, sys->getRequestorName(i));
}
+
bwRead = bytesRead / simSeconds;
bwInstRead = bytesInstRead / simSeconds;
bwWrite = bytesWritten / simSeconds;
// first we check if we already have a locked addr for this
// xc. Since each xc only gets one, we just update the
// existing record with the new address.
- list<LockedAddr>::iterator i;
+ std::list<LockedAddr>::iterator i;
for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
if (i->matchesContext(req)) {
DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
req->contextId(), paddr);
lockedAddrList.push_front(LockedAddr(req));
+ backdoor.invalidate();
}
// Only remove records when we succeed in finding a record for (xc, addr);
// then, remove all records with this address. Failed store-conditionals do
// not blow unrelated reservations.
- list<LockedAddr>::iterator i = lockedAddrList.begin();
+ std::list<LockedAddr>::iterator i = lockedAddrList.begin();
if (isLLSC) {
while (i != lockedAddrList.end()) {
DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
i->contextId, paddr);
ContextID owner_cid = i->contextId;
- ContextID requester_cid = pkt->req->contextId();
- if (owner_cid != requester_cid) {
- ThreadContext* ctx = system()->getThreadContext(owner_cid);
+ assert(owner_cid != InvalidContextID);
+ ContextID requestor_cid = req->hasContextId() ?
+ req->contextId() :
+ InvalidContextID;
+ if (owner_cid != requestor_cid) {
+ ThreadContext* ctx = system()->threads[owner_cid];
TheISA::globalClearExclusive(ctx);
}
i = lockedAddrList.erase(i);
tracePacket(System *sys, const char *label, PacketPtr pkt)
{
int size = pkt->getSize();
-#if THE_ISA != NULL_ISA
if (size == 1 || size == 2 || size == 4 || size == 8) {
- DPRINTF(MemoryAccess,"%s from %s of size %i on address %#x data "
- "%#x %c\n", label, sys->getMasterName(pkt->req->masterId()),
- size, pkt->getAddr(), pkt->getUintX(TheISA::GuestByteOrder),
+ ByteOrder byte_order = sys->getGuestByteOrder();
+ DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x data "
+ "%#x %c\n", label, sys->getRequestorName(pkt->req->
+ requestorId()), size, pkt->getAddr(),
+ size, pkt->getAddr(), pkt->getUintX(byte_order),
pkt->req->isUncacheable() ? 'U' : 'C');
return;
}
-#endif
DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n",
- label, sys->getMasterName(pkt->req->masterId()),
+ label, sys->getRequestorName(pkt->req->requestorId()),
size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C');
DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize());
}
assert(pkt->getAddrRange().isSubset(range));
- uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
+ uint8_t *host_addr = toHostAddr(pkt->getAddr());
if (pkt->cmd == MemCmd::SwapReq) {
if (pkt->isAtomicOp()) {
if (pmemAddr) {
- pkt->setData(hostAddr);
- (*(pkt->getAtomicOp()))(hostAddr);
+ pkt->setData(host_addr);
+ (*(pkt->getAtomicOp()))(host_addr);
}
} else {
std::vector<uint8_t> overwrite_val(pkt->getSize());
// keep a copy of our possible write value, and copy what is at the
// memory address into the packet
pkt->writeData(&overwrite_val[0]);
- pkt->setData(hostAddr);
+ pkt->setData(host_addr);
if (pkt->req->isCondSwap()) {
if (pkt->getSize() == sizeof(uint64_t)) {
condition_val64 = pkt->req->getExtraData();
- overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
+ overwrite_mem = !std::memcmp(&condition_val64, host_addr,
sizeof(uint64_t));
} else if (pkt->getSize() == sizeof(uint32_t)) {
condition_val32 = (uint32_t)pkt->req->getExtraData();
- overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
+ overwrite_mem = !std::memcmp(&condition_val32, host_addr,
sizeof(uint32_t));
} else
panic("Invalid size for conditional read/write\n");
}
if (overwrite_mem)
- std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize());
+ std::memcpy(host_addr, &overwrite_val[0], pkt->getSize());
assert(!pkt->req->isInstFetch());
TRACE_PACKET("Read/Write");
- numOther[pkt->req->masterId()]++;
+ stats.numOther[pkt->req->requestorId()]++;
}
} else if (pkt->isRead()) {
assert(!pkt->isWrite());
trackLoadLocked(pkt);
}
if (pmemAddr) {
- pkt->setData(hostAddr);
+ pkt->setData(host_addr);
}
TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
- numReads[pkt->req->masterId()]++;
- bytesRead[pkt->req->masterId()] += pkt->getSize();
+ stats.numReads[pkt->req->requestorId()]++;
+ stats.bytesRead[pkt->req->requestorId()] += pkt->getSize();
if (pkt->req->isInstFetch())
- bytesInstRead[pkt->req->masterId()] += pkt->getSize();
+ stats.bytesInstRead[pkt->req->requestorId()] += pkt->getSize();
} else if (pkt->isInvalidate() || pkt->isClean()) {
assert(!pkt->isWrite());
// in a fastmem system invalidating and/or cleaning packets
} else if (pkt->isWrite()) {
if (writeOK(pkt)) {
if (pmemAddr) {
- pkt->writeData(hostAddr);
- DPRINTF(MemoryAccess, "%s wrote %i bytes to address %x\n",
- __func__, pkt->getSize(), pkt->getAddr());
+ pkt->writeData(host_addr);
+ DPRINTF(MemoryAccess, "%s write due to %s\n",
+ __func__, pkt->print());
}
assert(!pkt->req->isInstFetch());
TRACE_PACKET("Write");
- numWrites[pkt->req->masterId()]++;
- bytesWritten[pkt->req->masterId()] += pkt->getSize();
+ stats.numWrites[pkt->req->requestorId()]++;
+ stats.bytesWritten[pkt->req->requestorId()] += pkt->getSize();
}
} else {
panic("Unexpected packet %s", pkt->print());
{
assert(pkt->getAddrRange().isSubset(range));
- uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start();
+ uint8_t *host_addr = toHostAddr(pkt->getAddr());
if (pkt->isRead()) {
if (pmemAddr) {
- pkt->setData(hostAddr);
+ pkt->setData(host_addr);
}
TRACE_PACKET("Read");
pkt->makeResponse();
} else if (pkt->isWrite()) {
if (pmemAddr) {
- pkt->writeData(hostAddr);
+ pkt->writeData(host_addr);
}
TRACE_PACKET("Write");
pkt->makeResponse();
// through printObj().
prs->printLabels();
// Right now we just print the single byte at the specified address.
- ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr);
+ ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *host_addr);
} else {
panic("AbstractMemory: unimplemented functional command %s",
pkt->cmdString());
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