mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / abstract_mem.cc

diff --git a/src/mem/abstract_mem.cc b/src/mem/abstract_mem.cc
index 1797deae83c0b8a265036090236e14c7e4ee4a4b..b41c82b0de037daf1754943fc8d0068ad5530eac 100644 (file)
--- a/src/mem/abstract_mem.cc
+++ b/src/mem/abstract_mem.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012 ARM Limited
+ * Copyright (c) 2010-2012,2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -42,13 +42,15 @@
  *          Andreas Hansson
  */
 
+#include "mem/abstract_mem.hh"
+
 #include <vector>
 
+#include "arch/locked_mem.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/LLSC.hh"
 #include "debug/MemoryAccess.hh"
-#include "mem/abstract_mem.hh"
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
 
@@ -271,13 +273,12 @@ AbstractMemory::checkLockedAddrList(PacketPtr pkt)
             if (i->addr == paddr) {
                 DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
                         i->contextId, paddr);
-                // For ARM, a spinlock would typically include a Wait
-                // For Event (WFE) to conserve energy. The ARMv8
-                // architecture specifies that an event is
-                // automatically generated when clearing the exclusive
-                // monitor to wake up the processor in WFE.
-                ThreadContext* ctx = system()->getThreadContext(i->contextId);
-                ctx->getCpuPtr()->wakeup(ctx->threadId());
+                ContextID owner_cid = i->contextId;
+                ContextID requester_cid = pkt->req->contextId();
+                if (owner_cid != requester_cid) {
+                    ThreadContext* ctx = system()->getThreadContext(owner_cid);
+                    TheISA::globalClearExclusive(ctx);
+                }
                 i = lockedAddrList.erase(i);
             } else {
                 i++;
@@ -386,6 +387,9 @@ AbstractMemory::access(PacketPtr pkt)
     } else if (pkt->isRead()) {
         assert(!pkt->isWrite());
         if (pkt->isLLSC()) {
+            assert(!pkt->fromCache());
+            // if the packet is not coming from a cache then we have
+            // to do the LL/SC tracking here
             trackLoadLocked(pkt);
         }
         if (pmemAddr)
@@ -395,18 +399,17 @@ AbstractMemory::access(PacketPtr pkt)
         bytesRead[pkt->req->masterId()] += pkt->getSize();
         if (pkt->req->isInstFetch())
             bytesInstRead[pkt->req->masterId()] += pkt->getSize();
-    } else if (pkt->isInvalidate()) {
+    } else if (pkt->isInvalidate() || pkt->isClean()) {
+        assert(!pkt->isWrite());
+        // in a fastmem system invalidating and/or cleaning packets
+        // can be seen due to cache maintenance requests
+
         // no need to do anything
-        // this clause is intentionally before the write clause: the only
-        // transaction that is both a write and an invalidate is
-        // WriteInvalidate, and for the sake of consistency, it does not
-        // write to memory.  in a cacheless system, there are no WriteInv's
-        // because the Write -> WriteInvalidate rewrite happens in the cache.
     } else if (pkt->isWrite()) {
         if (writeOK(pkt)) {
             if (pmemAddr) {
                 memcpy(hostAddr, pkt->getConstPtr<uint8_t>(), pkt->getSize());
-                DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n",
+                DPRINTF(MemoryAccess, "%s wrote %i bytes to address %x\n",
                         __func__, pkt->getSize(), pkt->getAddr());
             }
             assert(!pkt->req->isInstFetch());
@@ -415,7 +418,7 @@ AbstractMemory::access(PacketPtr pkt)
             bytesWritten[pkt->req->masterId()] += pkt->getSize();
         }
     } else {
-        panic("unimplemented");
+        panic("Unexpected packet %s", pkt->print());
     }
 
     if (pkt->needsResponse()) {