cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / addr_mapper.cc

diff --git a/src/mem/addr_mapper.cc b/src/mem/addr_mapper.cc
index 2f00205768e3e8408c5d40a504fc49c727d9cb8d..246c039eeecf1014c86b5270dad7c7401cbf6e68 100644 (file)
--- a/src/mem/addr_mapper.cc
+++ b/src/mem/addr_mapper.cc
@@ -40,7 +40,7 @@
 #include "mem/addr_mapper.hh"
 
 AddrMapper::AddrMapper(const AddrMapperParams* p)
-    : MemObject(p),
+    : SimObject(p),
       masterPort(name() + "-master", *this),
       slavePort(name() + "-slave", *this)
 {
@@ -53,23 +53,15 @@ AddrMapper::init()
         fatal("Address mapper is not connected on both sides.\n");
 }
 
-BaseMasterPort&
-AddrMapper::getMasterPort(const std::string& if_name, PortID idx)
+Port &
+AddrMapper::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name == "master") {
         return masterPort;
-    } else {
-        return MemObject::getMasterPort(if_name, idx);
-    }
-}
-
-BaseSlavePort&
-AddrMapper::getSlavePort(const std::string& if_name, PortID idx)
-{
-    if (if_name == "slave") {
+    } else if (if_name == "slave") {
         return slavePort;
     } else {
-        return MemObject::getSlavePort(if_name, idx);
+        return SimObject::getPort(if_name, idx);
     }
 }
 
@@ -116,16 +108,15 @@ AddrMapper::recvTimingReq(PacketPtr pkt)
 {
     Addr orig_addr = pkt->getAddr();
     bool needsResponse = pkt->needsResponse();
-    bool memInhibitAsserted = pkt->memInhibitAsserted();
+    bool cacheResponding = pkt->cacheResponding();
 
-    if (needsResponse && !memInhibitAsserted) {
+    if (needsResponse && !cacheResponding) {
         pkt->pushSenderState(new AddrMapperSenderState(orig_addr));
     }
 
     pkt->setAddr(remapAddr(orig_addr));
 
-    // Attempt to send the packet (always succeeds for inhibited
-    // packets)
+    // Attempt to send the packet
     bool successful = masterPort.sendTimingReq(pkt);
 
     // If not successful, restore the address and sender state