mem-cache: Create an address aware TempCacheBlk

[gem5.git] / src / mem / bridge.cc

diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 8a209e8b732af676c993d7c73f247a8d8830ac09..0c9e2c15a09c7d4736557d9b47d28eb43cbc653a 100644 (file)
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -48,9 +48,10 @@
  * and a slave through a request and response queue.
  */
 
+#include "mem/bridge.hh"
+
 #include "base/trace.hh"
 #include "debug/Bridge.hh"
-#include "mem/bridge.hh"
 #include "params/Bridge.hh"
 
 Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
@@ -60,8 +61,8 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
                                          std::vector<AddrRange> _ranges)
     : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
       delay(_delay), ranges(_ranges.begin(), _ranges.end()),
-      outstandingResponses(0), retryReq(false),
-      respQueueLimit(_resp_limit), sendEvent(*this)
+      outstandingResponses(0), retryReq(false), respQueueLimit(_resp_limit),
+      sendEvent([this]{ trySendTiming(); }, _name)
 {
 }
 
@@ -70,7 +71,8 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
                                            BridgeSlavePort& _slavePort,
                                            Cycles _delay, int _req_limit)
     : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
-      delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
+      delay(_delay), reqQueueLimit(_req_limit),
+      sendEvent([this]{ trySendTiming(); }, _name)
 {
 }