* and a slave through a request and response queue.
*/
+#include "mem/bridge.hh"
+
#include "base/trace.hh"
#include "debug/Bridge.hh"
-#include "mem/bridge.hh"
#include "params/Bridge.hh"
Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
std::vector<AddrRange> _ranges)
: SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
delay(_delay), ranges(_ranges.begin(), _ranges.end()),
- outstandingResponses(0), retryReq(false),
- respQueueLimit(_resp_limit), sendEvent(*this)
+ outstandingResponses(0), retryReq(false), respQueueLimit(_resp_limit),
+ sendEvent([this]{ trySendTiming(); }, _name)
{
}
BridgeSlavePort& _slavePort,
Cycles _delay, int _req_limit)
: MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
- delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
+ delay(_delay), reqQueueLimit(_req_limit),
+ sendEvent([this]{ trySendTiming(); }, _name)
{
}
{
}
-BaseMasterPort&
-Bridge::getMasterPort(const std::string &if_name, PortID idx)
+Port &
+Bridge::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "master")
return masterPort;
- else
- // pass it along to our super class
- return MemObject::getMasterPort(if_name, idx);
-}
-
-BaseSlavePort&
-Bridge::getSlavePort(const std::string &if_name, PortID idx)
-{
- if (if_name == "slave")
+ else if (if_name == "slave")
return slavePort;
else
// pass it along to our super class
- return MemObject::getSlavePort(if_name, idx);
+ return MemObject::getPort(if_name, idx);
}
void
DPRINTF(Bridge, "recvTimingReq: %s addr 0x%x\n",
pkt->cmdString(), pkt->getAddr());
- // if a cache is responding, sink the packet without further
- // action, also discard any packet that is not a read or a write
- if (pkt->cacheResponding() ||
- !(pkt->isWrite() || pkt->isRead())) {
- assert(!pkt->needsResponse());
- pendingDelete.reset(pkt);
- return true;
- }
+ panic_if(pkt->cacheResponding(), "Should not see packets where cache "
+ "is responding");
// we should not get a new request after committing to retry the
// current one, but unfortunately the CPU violates this rule, so
Tick
Bridge::BridgeSlavePort::recvAtomic(PacketPtr pkt)
{
+ panic_if(pkt->cacheResponding(), "Should not see packets where cache "
+ "is responding");
+
return delay * bridge.clockPeriod() + masterPort.sendAtomic(pkt);
}
// check the response queue
for (auto i = transmitList.begin(); i != transmitList.end(); ++i) {
- if (pkt->checkFunctional((*i).pkt)) {
+ if (pkt->trySatisfyFunctional((*i).pkt)) {
pkt->makeResponse();
return;
}
}
// also check the master port's request queue
- if (masterPort.checkFunctional(pkt)) {
+ if (masterPort.trySatisfyFunctional(pkt)) {
return;
}
}
bool
-Bridge::BridgeMasterPort::checkFunctional(PacketPtr pkt)
+Bridge::BridgeMasterPort::trySatisfyFunctional(PacketPtr pkt)
{
bool found = false;
auto i = transmitList.begin();
while (i != transmitList.end() && !found) {
- if (pkt->checkFunctional((*i).pkt)) {
+ if (pkt->trySatisfyFunctional((*i).pkt)) {
pkt->makeResponse();
found = true;
}