Bridge& _bridge,
BridgeMasterPort& _masterPort,
Cycles _delay, int _resp_limit,
- std::vector<Range<Addr> > _ranges)
+ std::vector<AddrRange> _ranges)
: SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
delay(_delay), ranges(_ranges.begin(), _ranges.end()),
outstandingResponses(0), retryReq(false),
{
}
-MasterPort&
-Bridge::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort&
+Bridge::getMasterPort(const std::string &if_name, PortID idx)
{
if (if_name == "master")
return masterPort;
return MemObject::getMasterPort(if_name, idx);
}
-SlavePort&
-Bridge::getSlavePort(const std::string &if_name, int idx)
+BaseSlavePort&
+Bridge::getSlavePort(const std::string &if_name, PortID idx)
{
if (if_name == "slave")
return slavePort;