mem: Fix guest corruption when caches handle uncacheable accesses

[gem5.git] / src / mem / bridge.cc

diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index ca3fde0ed60c599e81a83e308c2424a305f46fb4..bece5e6a13d6827669f766b0e6d4bff8cdf0c674 100644 (file)
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -56,8 +56,8 @@
 Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
                                          Bridge& _bridge,
                                          BridgeMasterPort& _masterPort,
-                                         int _delay, int _resp_limit,
-                                         std::vector<Range<Addr> > _ranges)
+                                         Cycles _delay, int _resp_limit,
+                                         std::vector<AddrRange> _ranges)
     : SlavePort(_name, &_bridge), bridge(_bridge), masterPort(_masterPort),
       delay(_delay), ranges(_ranges.begin(), _ranges.end()),
       outstandingResponses(0), retryReq(false),
@@ -68,7 +68,7 @@ Bridge::BridgeSlavePort::BridgeSlavePort(const std::string& _name,
 Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
                                            Bridge& _bridge,
                                            BridgeSlavePort& _slavePort,
-                                           int _delay, int _req_limit)
+                                           Cycles _delay, int _req_limit)
     : MasterPort(_name, &_bridge), bridge(_bridge), slavePort(_slavePort),
       delay(_delay), reqQueueLimit(_req_limit), sendEvent(*this)
 {
@@ -76,14 +76,15 @@ Bridge::BridgeMasterPort::BridgeMasterPort(const std::string& _name,
 
 Bridge::Bridge(Params *p)
     : MemObject(p),
-      slavePort(p->name + ".slave", *this, masterPort, p->delay, p->resp_size,
-                p->ranges),
-      masterPort(p->name + ".master", *this, slavePort, p->delay, p->req_size)
+      slavePort(p->name + ".slave", *this, masterPort,
+                ticksToCycles(p->delay), p->resp_size, p->ranges),
+      masterPort(p->name + ".master", *this, slavePort,
+                 ticksToCycles(p->delay), p->req_size)
 {
 }
 
-MasterPort&
-Bridge::getMasterPort(const std::string &if_name, int idx)
+BaseMasterPort&
+Bridge::getMasterPort(const std::string &if_name, PortID idx)
 {
     if (if_name == "master")
         return masterPort;
@@ -92,8 +93,8 @@ Bridge::getMasterPort(const std::string &if_name, int idx)
         return MemObject::getMasterPort(if_name, idx);
 }
 
-SlavePort&
-Bridge::getSlavePort(const std::string &if_name, int idx)
+BaseSlavePort&
+Bridge::getSlavePort(const std::string &if_name, PortID idx)
 {
     if (if_name == "slave")
         return slavePort;
@@ -140,7 +141,7 @@ Bridge::BridgeMasterPort::recvTimingResp(PacketPtr pkt)
 
     DPRINTF(Bridge, "Request queue size: %d\n", transmitList.size());
 
-    slavePort.schedTimingResp(pkt, curTick() + delay);
+    slavePort.schedTimingResp(pkt, bridge.clockEdge(delay));
 
     return true;
 }
@@ -170,7 +171,7 @@ Bridge::BridgeSlavePort::recvTimingReq(PacketPtr pkt)
             assert(outstandingResponses != respQueueLimit);
             ++outstandingResponses;
             retryReq = false;
-            masterPort.schedTimingReq(pkt, curTick() + delay);
+            masterPort.schedTimingReq(pkt, bridge.clockEdge(delay));
         }
     }
 
@@ -352,7 +353,7 @@ Bridge::BridgeSlavePort::recvRetry()
 Tick
 Bridge::BridgeSlavePort::recvAtomic(PacketPtr pkt)
 {
-    return delay + masterPort.sendAtomic(pkt);
+    return delay * bridge.clockPeriod() + masterPort.sendAtomic(pkt);
 }
 
 void