ruby: handle llsc accesses through CacheEntry, not CacheMemory

[gem5.git] / src / mem / bridge.cc

diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 5b925d1cb4d6dea572885c8e08e32344d5e16a83..ecaf6de0483dbce5b9ad4904d25bbdd2d3b4a119 100644 (file)
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -217,7 +217,7 @@ Bridge::BridgeMasterPort::schedTimingReq(PacketPtr pkt, Tick when)
 
     assert(transmitList.size() != reqQueueLimit);
 
-    transmitList.push_back(DeferredPacket(pkt, when));
+    transmitList.emplace_back(pkt, when);
 }
 
 
@@ -232,7 +232,7 @@ Bridge::BridgeSlavePort::schedTimingResp(PacketPtr pkt, Tick when)
         bridge.schedule(sendEvent, when);
     }
 
-    transmitList.push_back(DeferredPacket(pkt, when));
+    transmitList.emplace_back(pkt, when);
 }
 
 void