cpu: Apply the ARM TLB rework to the O3 checker CPU.

[gem5.git] / src / mem / bridge.hh

diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index bb772771725da02c38f934d2e491827561ad09b2..16b21addf4132bb4f98228b72785fc0918f9fe9d 100644 (file)
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -54,8 +54,9 @@
 #include <deque>
 
 #include "base/types.hh"
-#include "mem/mem_object.hh"
+#include "mem/port.hh"
 #include "params/Bridge.hh"
+#include "sim/clocked_object.hh"
 
 /**
  * A bridge is used to interface two different crossbars (or in general a
@@ -70,7 +71,7 @@
  * the bridge will delay accepting the packet until space becomes
  * available.
  */
-class Bridge : public MemObject
+class Bridge : public ClockedObject
 {
   protected:
 
@@ -316,12 +317,10 @@ class Bridge : public MemObject
 
   public:
 
-    virtual BaseMasterPort& getMasterPort(const std::string& if_name,
-                                          PortID idx = InvalidPortID);
-    virtual BaseSlavePort& getSlavePort(const std::string& if_name,
-                                        PortID idx = InvalidPortID);
+    Port &getPort(const std::string &if_name,
+                  PortID idx=InvalidPortID) override;
 
-    virtual void init();
+    void init() override;
 
     typedef BridgeParams Params;